RE: [SI-LIST] : IBIS vs HSpice

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From: Dunbar, Tony (tony_dunbar@mentorg.com)
Date: Fri Jan 19 2001 - 12:42:50 PST


Ken,

Just a slight correction or clarification, if I may: The IO delay of the
buffer model can be considered to be "provided" in a Quad model by way of
the time-to-VM parameter. In an IBIS model - a complete one, at least - the
related parameters are the test-circuit (Vref, Cref, Rref) and the Vmeas
parameter. These do not provide the IO delay, per se. Instead, they provide
for a capable IBIS simulator to use these to do a simulation to derive the
delay. Typically, the delay is reported as the time it takes the so-called
test waveform to cross the Vmeas level. This is the simulation equivalent
(or re-creation) of what the silicon vendor has done in order to provide the
delay numbers in the datasheet. Then, the IBIS simulator does the "real"
interconnect circuit simulation that, as you point out, is typically very
different from the test-load simulation - just as it is very different than
what the Si manufacturer did to also report his numbers. The actual real
circuit delay should then have the test-load result subtracted to obtain the
true loaded flight time.

I'll leave it to others to comment on the accuracy angle. I'm from one of
those SI tools vendor companies and I will be horribly hissed and booed if I
encroach into that domain!

Regards,
Tony

-----Original Message-----
From: Ken Wu [mailto:ken@force10networks.com]
Sent: Friday, January 19, 2001 1:00 PM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : IBIS vs HSpice

Talking about IBIS vs HSpice, I want to post one of my concerns: how
accurate it is using IBIS model to
do IO timing analysis? Typically in IBIS model the IO delay is provided with
test load while in really the
real load could be quite different from test load. With spice model, the IO
delay can be easily figured out
through spice simulation while with IBIS model, I don't know how accurate it
is when performing IO delay
analysis. Any thought on this?

Ken Z. Wu

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