From: Zabinski, Patrick J. (firstname.lastname@example.org)
Date: Fri Jan 19 2001 - 08:15:25 PST
Until now, I had not seen IBIS 3.2. I gave it a quick scan (particularly
section 7), and it looks like the standard (at least) has made
some significant improvements in the package description of
the model. Not sure who out there is responsible, but THANKS for
upgrading/updating the spec, and sorry if I offended anyone out there.
Now that the standard has been improved, have you seen
any evidence that the vendors/suppliers have been utilizing
this feature? If so, again THANKS to them.
All that said, the package model portion is still only a "portion"
of what I consider to be several shortcomings in the IBIS model
content, and as such, I much prefer to use transistor-level models
> Hi Pat,
> I agree with many, if not all, at least to some degree, of your points
> regarding IBIS.
> However, in particular I wanted to address your concern about package
> parasitics. This is a timely topic as I was going through,
> in excruciating
> detail, the "Package Modeling" section of the IBIS 3.2 spec
> yesterday. I'm
> wondering if you've had the opportunity to review this
> addition to IBIS.
> It seems to me that it may address at least some of your
> concerns. It seems
> to provide an implementation somewhat along the lines of a
> TOPSPEC type
> model in XTK (if your familiar with that). It provides the
> capability to
> specify transmission line length, coupling between pins,
> forking sections,
> You can provide RLC matrices in full, banded, or sparse formats.
> This is a somewhat new area for me, so I'm by no means
> proclaiming this a
> panacea for the issues you describe, but if you have an opportunity to
> review that portion of the IBIS 3.2 spec (the package model
> stuff is in
> Section 7) I'd be curious to get your thoughts on how well this might
> address your concerns on the package parasitic issues.
> Now, of course assuming this is an improvement, the challenge
> still lies in
> getting semiconductor folks to provide that level of detail (perhaps
> non-trivial for a 300, 400 or greater pin part?) and then
> getting all the
> various simulators to use the data in an intelligent manner.
> Again, I agree with your concerns on IBIS shortcomings
> (especially with
> respect to SSO phenomena). However, I guess I have an
> interest in hoping
> that it continues to improve because in many cases HSPICE (or
> any transistor
> level data) is simply not an option provided to us by many
> (actually, most)
> I'd be curious to get anybody's feedback on the shortcomings
> or strengths of
> the IBIS 3.2 package modeling capabilities.
> Jim P.
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