From: Zabinski, Patrick J. ([email protected])
Date: Fri Jan 19 2001 - 05:47:17 PST
We simulate using both IBIS (behavioral) and Hspice (transistor-level)
models. However, because we do not have an IBIS-only simulator,
we use Hspice for IBIS simulations. So, if I can read into your
question a bit, I think what you're really asking is "when do
we use IBIS *models* versus transistor-level models (regardless of
If my assumption is correct, then here's my response.
We use IBIS (behavioral) models only when we absolutely have to. If we
can get transistor-level models (what I believe you're calling
Hspice models), we use them.
When IBIS first starting becoming available, we talked about it
within our group, we studied the standards, and we studied the
information available within the models, and we determined IBIS
was sufficient for lower-frequency, lower-performance, more-forgiving
systems that we were dealing with. I haven't kept up to date
with all the IBIS developments, but I don't believe much
More specifically, packaging parasitics are MUCH more complicated
than the simple discrete L, R, and C models that IBIS allows. What
about crosstalk between package leads/traces? What about leads/traces
that are significantly long compared to an edge rate (where a
transmission line model is more appropriate)?
Also, what about SSN? Will an IBIS model behave differently
if I have have 1,000 simultaneous switching outputs (per ground
pin) vs just one SSO?
What about the non-ideal transistor behavior, like Miller
capacitance effects when the reflected wave hits the driver?
How do IBIS models get affected with different loads? What if
I don't supply the ideal/intended voltage supplies?
In short, after looking at IBIS models and standards, these issues
were not addressed to our satisfaction, and we've (i.e., all the engineers
in our group that I've talked with) have decided to avoid IBIS models
That said, for some technologies/vendors, IBIS models are the only
models available, and we're often stuck using them (within Hspice).
> Hi all,
> I'm curious to know who out there is running SI analysis in
> BOTH HSpice and
> IBIS, and what your thoughts and experiences are (good and bad).
> I'm most interested in the strategies people use to ensure they're
> simulating the same circuit in both simulators, how people
> models, and how well the two sets of simulation results are
> expected to
> Strategies for tool use (i.e. which kind of simulation do you
> use for which
> part of the design cycle) would also be a good topic for discussion.
> Comments (both public and private) are both welcome and appreciated.
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:39 PDT