From: Robert Khederian (RKhederian@whiteedc.com)
Date: Mon Jan 15 2001 - 12:58:41 PST
Does anyone have any insight into the following problem:
In order to maintain setup and hold times, we require various signals
(Address, Data, etc.) to have no more than a certain time delay from the
clock. Using the 6" = 1 nS rule of thumb, this calculates to some length.
For example, a typical rule might read
CLK length - 0.4 inches <= Address length <= CLK length +
We are using PADS to do the layout. It appears PAD's has no capability to
calculate the length of traces, specifically when the signals route to
several devices (i.e. an Address line routing to two memory devices). The
result is our CAD department is spending a lot of extra time manually adding
trace segment by trace segment. Do you know of any automated solutions that
could generate a report, i.e. any third party software vendors? How are
other companies handling these issues?
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