Re: [SI-LIST] : Copper balance

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From: Michael Nudelman (mnudelman@tellium.com)
Date: Wed Jan 10 2001 - 14:28:14 PST


I have a board, that had a hi-speed/digital in it; at some point I noticed the
"squares" and found no problem because of them.

My Hi-speeds are mostly in the innermost layers, and digitals are outside.

They kept the spacing of app. 250-300 mils between squares and the routing.

Mike.

Chris Padilla wrote:

> So they want a bunch of little squares (or some geometrical shape) of
> floating copper--that's fine and normal to do to prevent warpage of the
> fab. I still don't see much of a problem with this--it is floating and as
> long as it is far away from any component, spacing of the little squares
> shouldn't be too big of a deal but I have to honest in saying that I've
> never paid attention to the spacing of the little squares on my boards so I
> can't give you much advice on that subject.
>
> ----->Chris
>
> >Thanks Chris. The main problem is the PCB vendor wanted to have 40% copper
> >convereage on the layer and this implies small spacing between the
> >floating copper
> >geometries. Having squares 5x5 mm with the spacing 10 mm will give < 25%
> >copper
> >coverage; therefore less spacing is required. But what is the smallest
> >spacing and
> >what is the copper geometry to get 40% ?
> >
> >Dorin
> >
> >
> >
> >Chris Padilla wrote:
> >
> > > It is called thieving and I've found so signifcant EMI results positive or
> > > negative as a result. Just set a spacing criteria from any components like
> > > "no closer than 500 mils to any componenet or trace or via or whatever."
> > >
> > > If the board has lots of blank space to fill, the EMI team may wish to
> > > consider making embedded caps with the free space and copper flood
> > > depending on the reference plane nearby. I have found these caps to be of
> > > significant importance in controlling emissions and they are basically
> > "free!"
> > >
> > > Good Luck----->Chris
>
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