RE: [SI-LIST] : Copper balance

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From: Chris Padilla (cpad@cisco.com)
Date: Wed Jan 10 2001 - 13:38:43 PST


Hi Mark,

It is mostly a "if you have the space do/try it" kind of approach. Some of
the cost/chip reduction boards I work on have a surprising amount of empty
real estate and I have taken the opportunity to flood chunks of copper
there, stitch with the appropriate vias (ground or power), and Viola! You
have just created yourself a low-inductance, low-farad capacitor (compared
to a discrete one). Of course, pick layers on your stack-up that are very
close to the ground or power plane and then flood your copper and stitch
with power or ground vias, respectively, to create your capacitor.

----->Chris

>could you expound on this "embedded caps" methodology it sounds very
>interesting, but i am wondering what cost of real estate this method would
>incurr. it seems that in some of my high density designs i wouldn't be able
>to afford that kind of solution.
>
>thanx in advance
>Mark R. Stanford
>
>-----Original Message-----
>From: Chris Padilla [mailto:cpad@cisco.com]
>Sent: Wednesday, January 10, 2001 9:48 AM
>To: DORIN OPREA; SI-LIST
>Subject: Re: [SI-LIST] : Copper balance
>
>If the board has lots of blank space to fill, the EMI team may wish to
>consider making embedded caps with the free space and copper flood
>depending on the reference plane nearby. I have found these caps to be of
>significant importance in controlling emissions and they are basically
>"free!"
>
>Good Luck----->Chris

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