[SI-LIST] : Copper balance

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From: DORIN OPREA (dorin.oprea@alcatel.com)
Date: Wed Jan 10 2001 - 08:30:30 PST


I am working now on the copper balance issue we have on our PCBs. On the
outer layer beneath the converter a copper surface is required (E
shielding) which generates the copper balance issue on that particular
layer and also throughout the stack up. Thus, the unpopulated copper
space is filled with square or circle floating copper surfaces separated
in-between. These squares are overlapping throughout the stack up. The
question: what is the best copper geometry, its dimension and the
spacing between these geometries ?. Copper balance requires as much
copper as possible but EMC wants no floating copper and very weak
coupling between noisy areas such as converter and any functional
digital area.

Your help is really appreciated,

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