From: D. C. Sessions ([email protected])
Date: Tue Jan 09 2001 - 14:16:51 PST
On Friday 05 January 2001 12:50, Degerstrom, Michael J. wrote:
# Here are some comments/questions:
# 1) Can I assume that to realize your suggested impedance/voltage/current
# ranges that you would utilize some sort of process tuning
# approach such as that outlined in section 4 of JESDEC
# standard #67?
Gotta get those reflection coefficients down somehow. Some of the
processes I've seen have _very_ nice resistor tolerances, so it
might be possible to use them. By and large, however, some sort
of PVT compensation will be necessary.
# 2) Why 56 ohms nominal? Is it just to get your swing
# higher than with a 50 ohm system? Or is there another reason?
# I'm thinking that in the future designers will utilize chip
# on board packaging and microvia pcbs which may allow them
# to use all available route channels. Thus by raising Zo
# your crosstalk may become difficult to manage.
If anything, most of the technologies I'm seeing are tending towards
higher impedances. However, the 56 was just a first instance and
the intention is to provide for multiple standard impedances.
# 3) Why did you chose the dynamic impedance specs. for the
# terminator? Especially why limit the low end of the impedance?
# Couldn't a much lower terminator dV/dI value at VHIGH or VLOW be
# a good thing as noise coupled onto the signal will be
# reflected with an opposite polarity which allows for some
# degree of noise cancellation?
Not really. At the speeds we're heading for, it's essential that the
residual energy on the line be damped as quickly as possible. Also,
nonlinearities result in mixing between earlier and later pulses, which
is a Bad Thing. I'm conservative: I'll go for linear unless proven wrong.
# 4) Is there some way to leverage from the big benefit of LVDS
# where you reverse current through the load in effect allowing
# you to get the same signal swing with 1/2 the current when
# compared to non-LVDS approaches? I suspect that you just don't
# have the headroom to do LVDS. So if you need twice the .8v
# supply for LVDS then you end up burning the same power as an SLVS
# approach anyway.
Again, nonlinearity and delay. Pretty soon you have oodles
of residual energy flying around closing your eyes.
As for LVDS, it's about the most CMOS-hostile arrangement to come
along in quite a while. When I'm teaching, I call it "High-performance
signaling for 5.0 volt CMOS." If you're using anything newer than
350 nm CMOS processing, LVDS' high voltage requirements and lack
of headroom are hideously wasteful of potential performance.
# > -----Original Message-----
# > From: D. C. Sessions [mailto:[email protected]]
# > Sent: Thursday, January 04, 2001 11:24 AM
# > To: [email protected]
# > Subject: [SI-LIST] : Comments on proposed standard
# > A year ago I tried to start a thread on what a clean-sheet-of-paper
# > signaling standard would look like. Not much response, so I had to
# > wing it. Due to intense demand for short IC-to-IC connections at
# > absurd signaling rates, earlier this month I presented a proposed
# > standard for Scalable Low-Voltage Signaling to JEDEC's JC-16
# > committee on electrical interfaces.
# > A copy of the draft is at
# > http://www.primenet.com/~sessions/SLVS-400.pdf
# > Comments (or at least germane ones) invited.
# > --
# > | The race is not always to the swift, nor the battle to the strong. |
# > | Because the slow, feeble old codgers like me cheat. |
# > +--------------- D. C. Sessions <[email protected]> --------------+
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-- | The race is not always to the swift, nor the battle to the strong. | | Because the slow, feeble old codgers like me cheat. | +--------------- D. C. Sessions <[email protected]> --------------+
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