RE: [SI-LIST] : Comments on proposed standard

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From: Degerstrom, Michael J. (degerstrom.michael@mayo.edu)
Date: Fri Jan 05 2001 - 11:50:58 PST


D.C.,

Here are some comments/questions:

1) Can I assume that to realize your suggested impedance/voltage/current
ranges that you would utilize some sort of process tuning
approach such as that outlined in section 4 of JESDEC
standard #67?

2) Why 56 ohms nominal? Is it just to get your swing
higher than with a 50 ohm system? Or is there another reason?
I'm thinking that in the future designers will utilize chip
on board packaging and microvia pcbs which may allow them
to use all available route channels. Thus by raising Zo
your crosstalk may become difficult to manage.

3) Why did you chose the dynamic impedance specs. for the
terminator? Especially why limit the low end of the impedance?
Couldn't a much lower terminator dV/dI value at VHIGH or VLOW be
a good thing as noise coupled onto the signal will be
reflected with an opposite polarity which allows for some
degree of noise cancellation?

4) Is there some way to leverage from the big benefit of LVDS
where you reverse current through the load in effect allowing
you to get the same signal swing with 1/2 the current when
compared to non-LVDS approaches? I suspect that you just don't
have the headroom to do LVDS. So if you need twice the .8v
supply for LVDS then you end up burning the same power as an SLVS
approach anyway.

Mike

_______________________________________________________________
Mike Degerstrom Email: degerstrom.michael@mayo.edu
Mayo Clinic
200 1st Street SW
Gugg. Bldg. RM 1042A Phone: (507) 284-3292
Rochester, MN 55905 FAX: (507) 284-9171
WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html
_______________________________________________________________

> -----Original Message-----
> From: D. C. Sessions [mailto:si-list@lumbercartel.com]
> Sent: Thursday, January 04, 2001 11:24 AM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : Comments on proposed standard
>
>
> A year ago I tried to start a thread on what a clean-sheet-of-paper
> signaling standard would look like. Not much response, so I had to
> wing it. Due to intense demand for short IC-to-IC connections at
> absurd signaling rates, earlier this month I presented a proposed
> standard for Scalable Low-Voltage Signaling to JEDEC's JC-16
> committee on electrical interfaces.
>
> A copy of the draft is at
> http://www.primenet.com/~sessions/SLVS-400.pdf
>
> Comments (or at least germane ones) invited.
>
> --
> | The race is not always to the swift, nor the battle to the strong. |
> | Because the slow, feeble old codgers like me cheat. |
> +--------------- D. C. Sessions <dcs@lumbercartel.com> --------------+
>
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