From: Charles Hill (email@example.com)
Date: Fri Jan 05 2001 - 09:19:25 PST
I remember your intriguing request, and have now had some time for my ideas
to jell. Your draft is insightful and interesting. I think there are some
things you left out.
First, define the problem. "intense demand for short IC-to-IC connections
at absurd signaling rates" -- Problem: Transfer digital information between
ICs at ever higher speeds and accommodate trends in IC technology. Digital
information is sequences of symbols (bits), a discrete time, discrete
amplitude set. The transmission channel is continuous time, continuous
amplitude. So what you've left out or assumed is the translation between
these two domains, the detection process. There are two parts to this, the
amplitude and the time. Assuming a conventional amplitude thresholding
scheme, it leaves the time the clocking. So is that separate clocking, or
embedded clocking on a bus wide basis, or embedded clocking per bit? The
decision on the clocking also depends on what can be achieved in the IO
cell design and IC implementation, delays, deterministic jitter and so
forth (sidewall capacitance on interconnect is not getting lower and
neither is mutual inductance).
I'm interested in your insights into these considerations.
At 10:23 AM 1/4/01 -0700, D. C. Sessions wrote:
>A year ago I tried to start a thread on what a clean-sheet-of-paper
>signaling standard would look like. Not much response, so I had to
>wing it. Due to intense demand for short IC-to-IC connections at
>absurd signaling rates, earlier this month I presented a proposed
>standard for Scalable Low-Voltage Signaling to JEDEC's JC-16
>committee on electrical interfaces.
>A copy of the draft is at http://www.primenet.com/~sessions/SLVS-400.pdf
>Comments (or at least germane ones) invited.
>| The race is not always to the swift, nor the battle to the strong. |
>| Because the slow, feeble old codgers like me cheat. |
>+--------------- D. C. Sessions <firstname.lastname@example.org> --------------+
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