**From:** Eric Bogatin (*[email protected]*)

**Date:** Thu Jan 04 2001 - 13:44:44 PST

**Next message:**D. C. Sessions: "Re: [SI-LIST] : Comments on proposed standard"**Previous message:**Straube Associates: "[SI-LIST] : Senior Modeling Engineer Opportunity"

Hi folks-

Just a last minute reminder about the IMAPS Advanced Technology

Workshop next week on High Speed Digital Interconnects. You can find

more information at the url: http://www.imaps.org/hispeed2001prog.htm

see ya there!

--eric

**************************************

Eric Bogatin

CTO, Giga Test Labs

v: 913-393-1305

f: 913-393-1306

e: [email protected]

web: www.gigatest.com

**************************************

-----Original Message-----

From: [email protected]

[mailto:[email protected]]

Sent: Wednesday, January 03, 2001 7:00 PM

To: [email protected]

Subject: si-list-digest V1 #377

si-list-digest Wednesday, January 3 2001 Volume 01 :

Number 377

In this issue:

1.) RE: [SI-LIST] : SMA test connector PCB layout

"Larry Miller" <[email protected]>

2.) [SI-LIST] : simulation software

"Sean Murray" <[email protected]>

3.) [SI-LIST] : UltraCADs ESR Calculator *UPGRADED* (Resend)

Doug Brooks <[email protected]>

4.) [SI-LIST] : Re: si-list-digest V1 #376

"Ken Taylor" <[email protected]>

5.) [SI-LIST] : Differential Impedance Effects on Diff. Return Current

"Dill, Franz @ Celerity" <[email protected]>

6.) [SI-LIST] : RE: CDL file format

Doug Hopperstad <[email protected]>

7.) RE: [SI-LIST] : Differential Impedance Effects on Diff. Return Cu

rrent

"Ingraham, Andrew" <[email protected]>

8.) Re: [SI-LIST] : Differential Impedance Effects on Diff. Return

Current

Martyn Gaudion <[email protected]>

9.) Re: [SI-LIST] : Differential Impedance Effects on Diff. Return

Current

Doug Brooks <[email protected]>

10.) RE: [SI-LIST] : Differential Impedance Effects on Diff. Return Cu

rrent

"Chan, Michael" <[email protected]>

11.) RE: [SI-LIST] : Differential Impedance Effects on Diff. Return Cu

rrent

"Dill, Franz @ Celerity" <[email protected]>

12.) Re: [SI-LIST] : Differential Impedance Effects on Diff. Return

Current

Michael Nudelman <[email protected]>

13.) RE: [SI-LIST] : Differential Impedance Effects on Diff. Return Cu

rrent

"Dunbar, Tony" <[email protected]>

14.) Re: [SI-LIST] : RE: CDL file format

Alan Zhu <[email protected]>

----------------------------------------------------------------------

Date: Wed, 3 Jan 2001 11:33:41 -0800

From: "Larry Miller" <[email protected]>

Subject: RE: [SI-LIST] : SMA test connector PCB layout

This is a multi-part message in MIME format.

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charset="us-ascii"

Content-Transfer-Encoding: 7bit

Thanks! That's exactly what I ordered.

I agree about "caring about" discontinuities on TDR measurements.

However,

they are not so hidden from E-Z view in TDR as in a frequency-domain

measurement.

I've had a number of 1 Gb SERDES manufacturers' evaluation boards with

conventional SMA connectors with no problem (as well as the end-fire

setups)

but these were comparatively short trace lengths, etc., etc.

Larry Miller

-----Original Message-----

From: [email protected]

[mailto:[email protected]]On Behalf Of Bob Lewandowski

Sent: Wednesday, January 03, 2001 10:41 AM

To: Larry Miller

Cc: Si-List (E-mail)

Subject: Re: [SI-LIST] : SMA test connector PCB layout

Johnson Components has an "end launch" SMA that fits into a slot in

the

board edge, with a pin to contact a top surface microstrip trace.

It's

application is independent of board thickness. Johnson P/N

142-0721-88x.

Their web site is: http://www.johnsoncomp.com/sma.htm. A front view

picture is shown as "End Launch". The pin diameter is 30 mils, so

some

adjustment of the launch must be made for trace widths less than 30

mils.

Connection from the body to ground is also a significant issue with

this

type of connector. An edge plated slot that ties directly to the

ground

layers is best, both electrically and mechanically.

Your other choice, the 4 ground pin through hole type is difficult

to

match to FR-4 or similar Er materials. The best possible application

is to

a back side microstrip with minimum center conductor hole and pad

diameters.

No pads on inner layers. Clear ground pads on all layers back as far

as

possible, and drill holes after plating between the center pin and the

corner pins to reduce capacitance. With careful layout you can get a

reflection coefficient of better than 10%.

Incidentally, you should care about bad launches with a TDR because

a

large launch discontinuity masks (attenuates) downstream reflections.

---Bob Lewandowski

Vixel Corp.

Larry Miller wrote:

I need to make some measurements on PC boards up to 5 GHz using a

network

analyzer. In the past I didn't care that much because I was doing

TDR

measurements.

Unfortunately, the boards I will be looking at are too thick to

use the

"SMA

edge connector" trick.

Does anyone have a pointer to a good PCB footprint that will not

have

impedance discontinuities. The connector I want to mount is the

familiar

center pin + 4 ground pins vertical SMA style.

Thanks in advance for any help,

Larry Miller

**** To unsubscribe from si-list or si-list-digest: send e-mail to

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UNSUBSCRIBE

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">

<HTML><HEAD>

<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =

charset=3Dus-ascii">

<META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR></HEAD>

<BODY>

<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20

class=3D226322619-03012001>Thanks! That's exactly what I=20

ordered.</SPAN></FONT></DIV>

<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20

class=3D226322619-03012001></SPAN></FONT> </DIV>

<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =

class=3D226322619-03012001>I=20

agree about "caring about" discontinuities on TDR measurements.

However, =

they=20

are not so hidden from E-Z view in TDR as in a frequency-domain=20

measurement.</SPAN></FONT></DIV>

<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20

class=3D226322619-03012001></SPAN></FONT> </DIV>

<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =

class=3D226322619-03012001>I've=20

had a number of 1 Gb SERDES manufacturers' evaluation boards with =

conventional=20

SMA connectors with no problem (as well as the end-fire setups) but =

these were=20

comparatively short trace lengths, etc., etc.</SPAN></FONT></DIV>

<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20

class=3D226322619-03012001></SPAN></FONT> </DIV>

<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =

class=3D226322619-03012001>Larry=20

Miller</SPAN></FONT></DIV>

<BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px">

<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =

face=3DTahoma=20

size=3D2>-----Original Message-----<BR><B>From:</B>=20

[email protected] =

[mailto:[email protected]]<B>On=20

Behalf Of </B>Bob Lewandowski<BR><B>Sent:</B> Wednesday, January 03,

=

2001=20

10:41 AM<BR><B>To:</B> Larry Miller<BR><B>Cc:</B> Si-List=20

(E-mail)<BR><B>Subject:</B> Re: [SI-LIST] : SMA test connector

PCB=20

layout<BR><BR></DIV></FONT>Johnson Components has an "end launch"

SMA =

that=20

fits into a slot in the board edge, with a pin to contact a top =

surface=20

microstrip trace. It's application is independent of board=20

thickness. Johnson P/N 142-0721-88x. Their web site =

is: <A=20

=

href=3D"http://www.johnsoncomp.com/sma.htm">http://www.johnsoncomp.com

/sm=

a.htm.</A> =20

A front view picture is shown as "End Launch". The pin

diameter =

is 30=20

mils, so some adjustment of the launch must be made for trace widths

=

less than=20

30 mils. Connection from the body to ground is also a =

significant issue=20

with this type of connector. An edge plated slot that ties =

directly to=20

the ground layers is best, both electrically and mechanically.=20

<P>Your other choice, the 4 ground pin through hole type is

difficult =

to match=20

to FR-4 or similar Er materials. The best possible application

=

is to a=20

back side microstrip with minimum center conductor hole and pad=20

diameters. No pads on inner layers. Clear ground pads on

=

all=20

layers back as far as possible, and drill holes after plating

between =

the=20

center pin and the corner pins to reduce capacitance. With =

careful=20

layout you can get a reflection coefficient of better than 10%.=20

<P>Incidentally, you should care about bad launches with a TDR

because =

a large=20

launch discontinuity masks (attenuates) downstream reflections.=20

<P>---Bob Lewandowski <BR> Vixel Corp.=20

<P>Larry Miller wrote:=20

<BLOCKQUOTE TYPE=3D"CITE">I need to make some measurements on PC =

boards up to=20

5 GHz using a network <BR>analyzer. In the past I didn't care that

=

much=20

because I was doing TDR <BR>measurements.=20

<P>Unfortunately, the boards I will be looking at are too thick to

=

use the=20

"SMA <BR>edge connector" trick.=20

<P>Does anyone have a pointer to a good PCB footprint that will

not =

have=20

<BR>impedance discontinuities. The connector I want to mount is

the =

familiar=20

<BR>center pin + 4 ground pins vertical SMA style.=20

<P>Thanks in advance for any help,=20

<P>Larry Miller=20

<P>**** To unsubscribe from si-list or si-list-digest: send e-mail

=

to=20

<BR>[email protected] In the BODY of message put: =

UNSUBSCRIBE=20

<BR>si-list or UNSUBSCRIBE si-list-digest, for more help, put

HELP.=20

<BR>si-list archives are accessible at <A=20

href=3D"http://www.qsl.net/wb6tpu">http://www.qsl.net/wb6tpu>=20

<BR>****</P></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>

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------------------------------

Date: Wed, 3 Jan 2001 13:24:01 -0700

From: "Sean Murray" <[email protected]>

Subject: [SI-LIST] : simulation software

Anyone have any experience with either Speed2000 from sigrity or

Eagleware

RF? It appears the eagleware is a standalone system for doing

circuits, any

truth to that?

Sean Murray

General Manager

M&M Specialties, Inc.

1236 W. Southern Ave. #106

Tempe, AZ 85282

1-800-892-8760 x105

www.mmspec.com

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------------------------------

Date: Wed, 03 Jan 2001 11:47:33 -0800

From: Doug Brooks <[email protected]>

Subject: [SI-LIST] : UltraCADs ESR Calculator *UPGRADED* (Resend)

I apologize for the resend, but I got back about 10,000 "out of

Office"

responses last week. Bad week to send an announcement.

Besides, since then we made one minor improvement and now 3.01 is the

current version!

**********************************************************************

******

***********

At popular demand, UltraCAD's popular ESR calculator has been upgraded

to

Version 3.01

This is a FREE upgrade! All previous licenses will work with this new

version. Obtain the upgraded version from our web site at

http://www.ultracad.com

Changes (all of which have been requested by users) include:

*****************

This version is a Windows 9x Version and therefore recognizes long

filenames. It also is a little better than Version 2 at multitasking.

It is compatible with previous licenses. Previous input files need one

minor modification to be compatible with this version (the addition of

a

single line containing the string "startdata"). Refer to the updated

help

file for details

Comments may be entered and edited on the input setup screen, the

output

screen, and can be included in the input file. There is almost no

theoretical limit to the length of comment text, but there is a

practical

limit to what can be displayed on the screens.

The user can select either a white graphical background (for better

printing) or a gray background (for easier viewing). (Unfortunately,

you

can't select both, and you can't change a setting while a graph exists

on

an output form.)(3.01 adds a check-mark here to show current setting.)

There is improved output graphical information, now presented on two

screens (for users who like to use lower screen resolutions.)

There is provision to display major grids on the graph.

There is provision for printed output of the graph and the graphical

data.

*********************

Happy New Year to all from your friends at UltraCAD Design, Inc.

Doug Brooks

.

************************************************************

Doug Brooks' book "Electrical Engineering for the Non-Degreed

Engineer" is now available. See our web site for details.

.

Doug Brooks, President [email protected]

UltraCAD Design, Inc. http://www.ultracad.com

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------------------------------

Date: Wed, 3 Jan 2001 14:09:56 -0800

From: "Ken Taylor" <[email protected]>

Subject: [SI-LIST] : Re: si-list-digest V1 #376

Chris, what you propose is very doable. At some point you have to

trade

theory and purity for connectivity, and both Tek and HP (now Agilent)

as

well as others long past like Philips and Dolch etc. have done it for

years

with various woven ribbon configurations ending in pairs.

Regards, Ken.

Ken Taylor

Polar Instruments, Portland, OR, USA.

+1 503 356-9001

[email protected]

* > Date: Tue, 2 Jan 2001 20:47:07 -0500
*

*> From: "Christopher R. Johnson" <[email protected]>
*

*> Subject: [SI-LIST] : Resistive probe and twisted pair revisited
*

*>
*

*> This is a multi-part message in MIME format.
*

*>
*

*> - ------=_NextPart_000_0104_01C074FD.2B907810
*

*> Content-Type: text/plain;
*

*> charset="iso-8859-1"
*

*> Content-Transfer-Encoding: quoted-printable
*

*>
*

*> It seems that the biggest down side to using twisted pair for the =
*

*> resistive probe is the lack of the coaxial shield for noise
*

reduction =

*> and impedance stabilization.
*

*>
*

*> The actual application is for a very low cost relatively high =
*

*> performance logic analyzer (500 MHz sample rate), so there must be
*

16 =

*> probes.
*

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------------------------------

Date: Wed, 3 Jan 2001 14:20:09 -0800

From: "Dill, Franz @ Celerity" <[email protected]>

Subject: [SI-LIST] : Differential Impedance Effects on Diff. Return

Current

All,

Please excuse my 'newbie-like' questions, my inclusion in this mailing

list

is more for curiosity and personal advancement/understanding than as a

profession.

First, is this statement valid?

- - In a differential pair, one 'leg' of a signal's return current

path is

through the complementary 'leg' of a differential pair and not through

the

ground or power planes (Assuming equal trace lengths, Zo=50

single-ended,

Zo=100 diff. impedance - using ECL logic as an example).

Now, assuming the above statement is true:

If the differential impedance is NOT 100 Ohms (Differential traces NOT

routed differentially) how does this effect the return current path?

Does

the return current begin to flow through the ground and power planes

rather

than through the differential pair?

Thanks SI gurus!

Franz.

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------------------------------

Date: Wed, 3 Jan 2001 17:01:10 -0600

From: Doug Hopperstad <[email protected]>

Subject: [SI-LIST] : RE: CDL file format

I asked my vender for IBIS or SPICE models for one of their devices

and was

sent a "CDL" formatted file. The email indicated that the file

contains all

the information about the sub-circuits and should be able to be

converted to

IBIS. Here is my question, what is a CDL file and has anyone converted

it to

either an IBIS or SPICE model? Any feedback would be greatly welcomed.

Here is some information I found on web regarding CDL files: A CDL

(network

Common data form Description Language) file is an ASCII description of

the

binary data in a netCDF file that is designed to be easily read by

humans.

Doug Hopperstad

Qlogic

[email protected]

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------------------------------

Date: Wed, 3 Jan 2001 18:00:03 -0500

From: "Ingraham, Andrew" <[email protected]>

Subject: RE: [SI-LIST] : Differential Impedance Effects on Diff.

Return Cu rrent

*> First, is this statement valid?
*

*> - In a differential pair, one 'leg' of a signal's return current
*

path is

*> through the complementary 'leg' of a differential pair and not
*

through the

*> ground or power planes (Assuming equal trace lengths, Zo=50
*

single-ended,

*> Zo=100 diff. impedance - using ECL logic as an example).
*

The return current flows through any nearby conductors; at high

frequencies,

most of the return current is through the closest conductor(s).

If this happens to be a reference plane, that's where it goes. If it

is the

complementary signal line, that's where it goes.

You can construct a differential pair out of two separate traces that

are

far apart from one another, in which case each one has a return

current in

its neighboring plane(s) (which happens to roughly equal the signal

current

in the opposite trace). The two currents in the plane are opposite

and

would cancel at low frequencies, but at high frequencies the return

current

is confined to the space "under" each trace and does not cancel, so in

effect you have a circulating loop of return current in the planes, of

magnitude equal to the signal current.

In the other extreme, you can also construct a differential pair out

of two

traces that are tightly coupled to one another (such as broadside

coupled)

and further away from reference planes, in which case each line's

"return"

current is the other line's signal current and there is no significant

current in the planes.

Differential pairs have both a differential (odd-mode) impedance and a

common-mode (even-mode) impedance. The two examples could have the

same

differential impedance but very different even-mode impedances.

If you route two 50 ohm traces over ground planes, you'd get slightly

less

than 100 ohms differential impedance. To get closer to 100 ohms, you

need

to keep them further apart, in which case most of the return current

remains

in the planes. To get more cancellation of the plane's return

current, you

need them closer together, which reduces the differential impedance

(you

would need to use >50 ohm traces to get 100 ohms differential).

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------------------------------

Date: Wed, 03 Jan 2001 23:03:28 +0000

From: Martyn Gaudion <[email protected]>

Subject: Re: [SI-LIST] : Differential Impedance Effects on Diff.

Return Current

Dear Franz,

Yes you are correct, if a differential pair are routed with very close

spacing the return current

is through the other "leg" of the pair.

Move the spacing further apart and if you are between planes you reach

a point

where there is no coupling between the pair - and all the return

current is

through the ground and power planes. Once you reach this spacing you

have lost

many of the benefits of the differential pair.

You can see where the coupling reduces to zero by using a field solver

like Polar CITS25, - put some numbers in for a differential pair then

move

the pair further apart until they are uncoupled..

There is further information in the newly revised booklet on

controlled

impedance

PCBs which you can download as a PDF from www.polarinstruments.com

Kind regards

Martyn Gaudion

Polar Instruments

Tel + 44 1481 253081

email [email protected]

At 14:20 03/01/01 -0800, you wrote:

*>All,
*

*>
*

*>Please excuse my 'newbie-like' questions, my inclusion in this
*

mailing list

*>is more for curiosity and personal advancement/understanding than as
*

a

*>profession.
*

*>
*

*>First, is this statement valid?
*

*>- In a differential pair, one 'leg' of a signal's return current path
*

is

*>through the complementary 'leg' of a differential pair and not
*

through the

*>ground or power planes (Assuming equal trace lengths, Zo=50
*

single-ended,

*>Zo=100 diff. impedance - using ECL logic as an example).
*

*>
*

*>Now, assuming the above statement is true:
*

*>If the differential impedance is NOT 100 Ohms (Differential traces
*

NOT

*>routed differentially) how does this effect the return current path?
*

Does

*>the return current begin to flow through the ground and power planes
*

rather

*>than through the differential pair?
*

*>
*

*>Thanks SI gurus!
*

*>
*

*>Franz.
*

*>
*

*>**** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*>[email protected] In the BODY of message put: UNSUBSCRIBE
*

*>si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
*

*>si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*>****
*

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------------------------------

Date: Wed, 03 Jan 2001 15:12:09 -0800

From: Doug Brooks <[email protected]>

Subject: Re: [SI-LIST] : Differential Impedance Effects on Diff.

Return Current

At 02:20 PM 1/3/01 -0800, you wrote:

*>All,
*

*>
*

*>Please excuse my 'newbie-like' questions, my inclusion in this
*

mailing list

*>is more for curiosity and personal advancement/understanding than as
*

a

*>profession.
*

*>
*

*>First, is this statement valid?
*

*>- In a differential pair, one 'leg' of a signal's return current path
*

is

*>through the complementary 'leg' of a differential pair and not
*

through the

*>ground or power planes (Assuming equal trace lengths, Zo=50
*

single-ended,

*>Zo=100 diff. impedance - using ECL logic as an example).
*

*>
*

*>Now, assuming the above statement is true:
*

*>If the differential impedance is NOT 100 Ohms (Differential traces
*

NOT

*>routed differentially) how does this effect the return current path?
*

Does

*>the return current begin to flow through the ground and power planes
*

rather

*>than through the differential pair?
*

First, change the question slightly to: If the SINGLE ENDED TRACE

IMPEDANCES ARE NOT EXACTLY MATCHED (it doesn't particularly matter

what the

values are, it matters whether they are matched) then the currents

down

them won't be exactly equal (and opposite) and therefore the

difference in

current will flow through (through the device and to) another return

path

(presumably ground).

Doug Brooks

.

************************************************************

Doug Brooks' book "Electrical Engineering for the Non-Degreed

Engineer" is now available. See our web site for details.

.

Doug Brooks, President [email protected]

UltraCAD Design, Inc. http://www.ultracad.com

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------------------------------

Date: Wed, 3 Jan 2001 17:37:14 -0600

From: "Chan, Michael" <[email protected]>

Subject: RE: [SI-LIST] : Differential Impedance Effects on Diff.

Return Cu rrent

Andy:

If you have a tightly coupled pairs but there is also a reference

plane

near by

and if in this case the separation between the pair is about the same

as the

distance

of the traces to the reference plane then will the image current for

each

trace still

shows up on the trace or they will show up mostly on the reference

plane?

Regards,

Michael Chan

- -----Original Message-----

From: Ingraham, Andrew

Sent: Wednesday, January 03, 2001 5:00 PM

To: 'Dill, Franz @ Celerity'

Cc: 'SI-Mailing List'

Subject: RE: [SI-LIST] : Differential Impedance Effects on Diff.

Return

Cu rrent

*> First, is this statement valid?
*

*> - In a differential pair, one 'leg' of a signal's return current
*

path is

*> through the complementary 'leg' of a differential pair and not
*

through the

*> ground or power planes (Assuming equal trace lengths, Zo=50
*

single-ended,

*> Zo=100 diff. impedance - using ECL logic as an example).
*

The return current flows through any nearby conductors; at high

frequencies,

most of the return current is through the closest conductor(s).

If this happens to be a reference plane, that's where it goes. If it

is the

complementary signal line, that's where it goes.

You can construct a differential pair out of two separate traces that

are

far apart from one another, in which case each one has a return

current in

its neighboring plane(s) (which happens to roughly equal the signal

current

in the opposite trace). The two currents in the plane are opposite

and

would cancel at low frequencies, but at high frequencies the return

current

is confined to the space "under" each trace and does not cancel, so in

effect you have a circulating loop of return current in the planes, of

magnitude equal to the signal current.

In the other extreme, you can also construct a differential pair out

of two

traces that are tightly coupled to one another (such as broadside

coupled)

and further away from reference planes, in which case each line's

"return"

current is the other line's signal current and there is no significant

current in the planes.

Differential pairs have both a differential (odd-mode) impedance and a

common-mode (even-mode) impedance. The two examples could have the

same

differential impedance but very different even-mode impedances.

If you route two 50 ohm traces over ground planes, you'd get slightly

less

than 100 ohms differential impedance. To get closer to 100 ohms, you

need

to keep them further apart, in which case most of the return current

remains

in the planes. To get more cancellation of the plane's return

current, you

need them closer together, which reduces the differential impedance

(you

would need to use >50 ohm traces to get 100 ohms differential).

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------------------------------

Date: Wed, 3 Jan 2001 16:04:32 -0800

From: "Dill, Franz @ Celerity" <[email protected]>

Subject: RE: [SI-LIST] : Differential Impedance Effects on Diff.

Return Cu rrent

Andy,

Are the following observations then true?

If I wanted to isolate a ECL clock signal's return current path to the

diff.

complementary rail I would INCREASE the distance of both traces from

the

signal's reference plane but RETAIN the 100 Ohm differential impedance

and

terminate accordingly - making the diff. complementary rail the least

inductive path.

(Thinking about this - it's quite intuitive)

In a real-world situation where spacing to ref. plane is 2 mils

(Buried Cap)

with diff. spacing of 11 mils a majority of the return current will

run

through the ref. plane with a small amount through the complementary

diff.

rail. (Assumes no other near-by traces)

Franz.

- -----Original Message-----

From: Ingraham, Andrew [mailto:[email protected]]

Sent: Wednesday, January 03, 2001 3:00 PM

To: 'Dill, Franz @ Celerity'

Cc: 'SI-Mailing List'

Subject: RE: [SI-LIST] : Differential Impedance Effects on Diff.

Return

Cu rrent

*> First, is this statement valid?
*

*> - In a differential pair, one 'leg' of a signal's return current
*

path is

*> through the complementary 'leg' of a differential pair and not
*

through the

*> ground or power planes (Assuming equal trace lengths, Zo=50
*

single-ended,

*> Zo=100 diff. impedance - using ECL logic as an example).
*

The return current flows through any nearby conductors; at high

frequencies,

most of the return current is through the closest conductor(s).

If this happens to be a reference plane, that's where it goes. If it

is the

complementary signal line, that's where it goes.

You can construct a differential pair out of two separate traces that

are

far apart from one another, in which case each one has a return

current in

its neighboring plane(s) (which happens to roughly equal the signal

current

in the opposite trace). The two currents in the plane are opposite

and

would cancel at low frequencies, but at high frequencies the return

current

is confined to the space "under" each trace and does not cancel, so in

effect you have a circulating loop of return current in the planes, of

magnitude equal to the signal current.

In the other extreme, you can also construct a differential pair out

of two

traces that are tightly coupled to one another (such as broadside

coupled)

and further away from reference planes, in which case each line's

"return"

current is the other line's signal current and there is no significant

current in the planes.

Differential pairs have both a differential (odd-mode) impedance and a

common-mode (even-mode) impedance. The two examples could have the

same

differential impedance but very different even-mode impedances.

If you route two 50 ohm traces over ground planes, you'd get slightly

less

than 100 ohms differential impedance. To get closer to 100 ohms, you

need

to keep them further apart, in which case most of the return current

remains

in the planes. To get more cancellation of the plane's return

current, you

need them closer together, which reduces the differential impedance

(you

would need to use >50 ohm traces to get 100 ohms differential).

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------------------------------

Date: Wed, 03 Jan 2001 19:18:08 -0500

From: Michael Nudelman <[email protected]>

Subject: Re: [SI-LIST] : Differential Impedance Effects on Diff.

Return Current

Franz:

This depends how you routed your pairs.

If you have un-coupled pair (two independent transmission lines) - the

ret.

currents will flow into the ref. plane(s).

If the pair is tightly coupled - almost all current will flow in the

opposite

conductor.

If it is loosely coupled, the current will be shared between the plane

and the

opposite conductor.

I simulated some of the broadside-coupled pairs I use; when I removed

planes,

the impedance changed about 15%, which means also, that the pair was

tightly

coupled and most current would flow in the opposite conductor versus

the ref.

plane.

So, if you have 2 100Ohms lines, the resulting impedance is <= 50Ohm.

The

tighter the coupling, the lower the impedance will be.

And - the fast changing current always tries the least inductance

path. Which

alleviates understanding of where and why it will flow. For example,

all other

things being equal, the current will go in the closest parallel

conductor

(plane or wire) to minimize the loop area (the inductance is

proportional to

the loop area).

Mike.

"Dill, Franz @ Celerity" wrote:

*> All,
*

*>
*

*> Please excuse my 'newbie-like' questions, my inclusion in this
*

mailing list

*> is more for curiosity and personal advancement/understanding than as
*

a

*> profession.
*

*>
*

*> First, is this statement valid?
*

*> - In a differential pair, one 'leg' of a signal's return current
*

path is

*> through the complementary 'leg' of a differential pair and not
*

through the

*> ground or power planes (Assuming equal trace lengths, Zo=50
*

single-ended,

*> Zo=100 diff. impedance - using ECL logic as an example).
*

*>
*

*> Now, assuming the above statement is true:
*

*> If the differential impedance is NOT 100 Ohms (Differential traces
*

NOT

*> routed differentially) how does this effect the return current path?
*

Does

*> the return current begin to flow through the ground and power planes
*

rather

*> than through the differential pair?
*

*>
*

*> Thanks SI gurus!
*

*>
*

*> Franz.
*

*>
*

*> **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*> [email protected] In the BODY of message put: UNSUBSCRIBE
*

*> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
*

*> si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*> ****
*

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------------------------------

Date: Wed, 3 Jan 2001 16:23:01 -0800

From: "Dunbar, Tony" <[email protected]>

Subject: RE: [SI-LIST] : Differential Impedance Effects on Diff.

Return Cu rrent

Franz,

In the ideal world, the first statement is valid. It is also usually

the

intended operation that the designer is aiming for and assuming when a

(tightly-coupled) diff-pair is implemented. Any signal will always

find its

way to a destination via the path of least impedance. This fact is

most

often related to when considering the signal's return path. If the

return

path through the power/ground planes offers a lower impedance path

than any

other path, including the complementary trace of a diff-pair, then

that

least-impedance path will be used at any points along the way or way

back.

I think a key thing to keep in mind is to consider this in the

electromagnetic realm rather than simply the AC since it is the

electromagnetic coupling from the primary signal conductor to the

neigboring

conductive elements within the electromagnetic field that dictates

what the

return path elements will be.

I was going to move on and separately address your follow-up question

but I

think I may have covered that already with the answer above (??).

Regards,

Tony

- -----Original Message-----

From: Dill, Franz @ Celerity [mailto:[email protected]]

Sent: Wednesday, January 03, 2001 4:20 PM

To: 'SI-Mailing List'

Subject: [SI-LIST] : Differential Impedance Effects on Diff. Return

Current

All,

Please excuse my 'newbie-like' questions, my inclusion in this mailing

list

is more for curiosity and personal advancement/understanding than as a

profession.

First, is this statement valid?

- - In a differential pair, one 'leg' of a signal's return current

path is

through the complementary 'leg' of a differential pair and not through

the

ground or power planes (Assuming equal trace lengths, Zo=50

single-ended,

Zo=100 diff. impedance - using ECL logic as an example).

Now, assuming the above statement is true:

If the differential impedance is NOT 100 Ohms (Differential traces NOT

routed differentially) how does this effect the return current path?

Does

the return current begin to flow through the ground and power planes

rather

than through the differential pair?

Thanks SI gurus!

Franz.

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------------------------------

Date: Wed, 3 Jan 2001 16:25:18 -0800 (PST)

From: Alan Zhu <[email protected]>

Subject: Re: [SI-LIST] : RE: CDL file format

Doug,

CDL stands for Circuit Description Language. It's meant to be used for

LVS (layout versus schematic) checking. It IS in Spice format. You can

use it directly in your Spice simulations. ( You may have to modify

some

of the parameters as some of them, for example the channel length, are

so

large that they are out of valid parameter range of the device model).

Alan Zhu

LightSand Communications

*>From: Doug Hopperstad <[email protected]>
*

*>To: [email protected]
*

*>Subject: [SI-LIST] : RE: CDL file format
*

*>Date: Wed, 3 Jan 2001 17:01:10 -0600
*

*>MIME-Version: 1.0
*

*>
*

*>I asked my vender for IBIS or SPICE models for one of their devices
*

and was

*>sent a "CDL" formatted file. The email indicated that the file
*

contains all

*>the information about the sub-circuits and should be able to be
*

converted to

*>IBIS. Here is my question, what is a CDL file and has anyone
*

converted it to

*>either an IBIS or SPICE model? Any feedback would be greatly
*

welcomed.

*>
*

*>Here is some information I found on web regarding CDL files: A CDL
*

(network

*>Common data form Description Language) file is an ASCII description
*

of the

*>binary data in a netCDF file that is designed to be easily read by
*

humans.

*>
*

*>Doug Hopperstad
*

*>Qlogic
*

*>[email protected]
*

*>
*

*>
*

*>
*

*>
*

*>**** To unsubscribe from si-list or si-list-digest: send e-mail to
*

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*>si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*>****
*

*>
*

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------------------------------

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