From: Ingraham, Andrew ([email protected])
Date: Wed Dec 27 2000 - 06:46:44 PST
The previous replies are correct.
PCI uses what is called "reflected wave" rather than "incident wave"
switching. This means that the waveform might not switch all the way from
0% to 100% initially, until reflections off the open ends occur, so plateaus
and glitches may happen, especially (but not only) for receivers not on the
ends of the bus. Monotonicity is not a requirement.
For bussed signals, 33MHz PCI gives them 10ns to propagate and settle to a
valid level. During that time, anything goes; signals may bounce, sit at
threshold, etc. That is OK because none of these signals are sampled until
the next clock rising edge. "All signals are sampled on the rising edge of
the clock. Each signal has a setup and hold aperture with respect to the
rising clock edge, in which transitions are not allowed. Outside this
aperture, signal values or transitions have no significance."
Clock and Reset are exceptions and must have clean edges.
The waveform you show is actually rather good for an AD signal.
A typically more troublesome situation is when the driver is stronger
(best-case), the rising edge overshoots 3.3V by a couple of volts (I see you
are looking at a "5V signaling" bus so there is no clamp at 3.3V), then
swings back down to 1V or so, a few nanoseconds later. Falling edges can
overshoot and ring for several nanoseconds. It can get ugly. If all your
bussed waveforms look as good as your example, you are in very good shape.
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