From: Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Date: Fri Dec 22 2000 - 04:54:57 PST
> Can the on-chip inductance seen by a core
> power supply be determined from an IBIS model?
> Is it simply the parallel combination of all
> the inductances of the power/ground pins?
> Or do the package parasitics have to be
> figured in as well (assuming all the above
> info is in the model)?
Be very careful when thinking about inductance. What is the inductance you
want to know? That seen between on-chip Vdd and on-chip Vss? That is, from
the on-chip Vdd node, through the package POWER pins, POWER ac-shorted to
GND on the PC board, back through the package GND pins, and back to on-chip
Vss? (Always make a closed loop.)
One reason why this gets hairy, is that the (partial) inductances of each
pin interact with one another, due to their mutual inductances, and you
can't just parallel them like you would with resistances. Basic IBIS
datasheets don't have the mutuals.
A more complex [Package Model] definition might give you a bit more to go
Two POWER pins that are close to one another and in parallel, would have
more inductance than half of either one alone. Five pins that are really
close together, could be little better than one pin alone ... not very
likely, but possible.
A POWER pin and a GND pin that are close to one another, could have a total
(loop) inductance that is LESS than either one alone, even though they are
effectively in series with one another and you'd be tempted to add them.
I suppose you could say that the worst-case upper bound on the total loop
inductance from Vdd to Vss, is the sum of the (partial) inductances of ONE
POWER pin and ONE GND pin, which you can get from the IBIS datasheet ...
assuming that all POWER pins are tightly coupled and all GND pins are
tightly coupled but there is no coupling between the two groups; or that
locality on the die removes other POWER and GND pins from consideration.
But that doesn't tell you much.
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