RE: [SI-LIST] : IBIS model (Package parasitics)

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From: George Borkowicz (jbor@nortelnetworks.com)
Date: Wed Dec 20 2000 - 08:38:48 PST


Henry,

A couple more warnings against package included concept.

To second Stephen's position, the VT curves may potentially be
not accurate or even impossible to extract or of such a shape that
the simulator will get in trouble and produce inaccurate results.

In one scenario, including package parasitics in VT curves extraction
will most likely result in the curves with an oscillatory component.
To generate valid VT curve you now have to wait these oscillations
out until the steady state is reached. This may take much, much longer
(depending on the package parasitics and where they appear)
then a plain, no package transition. Now you also have to
describe these oscillations and the transition precisely with
max 100 points. See where that leads?

Your timing measurements may be also off since some reference
circuits that rely on pure buffer will not be available.

So, if you have such a model and it is shown to work for you
(correlated) then sure, go ahead and use it. If you are
contemplating building one yourself please, don't...

gjb

> -----Original Message-----
> From: LEE,HENRY (A-SanJose,ex1) [SMTP:henry_lee2@agilent.com]
> Sent: Tuesday, December 19, 2000 12:11 PM
> To: 'Peters, Stephen'; si-list@silab.eng.sun.com
> Subject: RE: [SI-LIST] : IBIS model (Package parasitics)
>
> Stephen,
>
> that is exactly what I mean. So what you are saying is that, if
> I include the parasitics only while the IBIS model is built, there will
> be a big difference compared to if I exclude it during model build and
> include it in the IBIS model file (as R_pkg, etc). I expected this
> difference in the model files but what I really wanted to ask was when
> I use these 2 models in an analysis tool like XTK, will I see any
> difference.?
> After all, for a user of the IBIS models, this is what matters.
>
> I take it from the other respondents that the answer is no, there is no
> difference. If this is the case, then we could use either method to
> handle
> the parasitics of the package.
>
>
>
>
> > -----Original Message-----
> > From: Peters, Stephen [mailto:stephen.peters@intel.com]
> > Sent: Friday, December 15, 2000 4:14 PM
> > To: 'henry_lee2@agilent.com'; si-list@silab.eng.sun.com
> > Subject: RE: [SI-LIST] : IBIS model (Package parasitics)
> >
> >
> >
> > Hi Henry:
> >
> > If you are referring to the simulations used to extract
> > data to build a
> > model, then including the package makes a BIG difference, at
> > least in the
> > case of V-T tables. The V-T waveform tables are intended to
> > capture the
> > switching and overlap characteristics of the pull-up and pull-down
> > transistors such that the simulator can extract the pertinent
> > characteristics of the CMOS transistors themselves. If you
> > add in the dV/dt
> > and dI/dt effects of capacitance and inductance then all bets
> > are off -- it
> > is very difficult (if not impossible) to de-imbed the
> > transistor switching
> > data. Therefore, you should always take the [Ramp] and waveform data
> > without the effects of packaging included.
> >
> > Regards,
> > Stephen Peters
> > Intel Corp.
> >
> > -----Original Message-----
> > From: henry_lee2@agilent.com [mailto:henry_lee2@agilent.com]
> > Sent: Friday, December 15, 2000 3:24 PM
> > To: si-list@silab.eng.sun.com
> > Subject: [SI-LIST] : IBIS model (Package parasitics)
> >
> >
> > Hi
> >
> > In regard to IBIS models, it seems the recommendation is to remove the
> > parasitics of the package during simulation and include it in the
> > model file itself. I supposed an alternative would be to leave
> > it in during simulation and set the parasitics as zero in the
> > model file. Can someone please clarify the differences, if any,
> > between these two methods. Thanks in advance
> >
> > -Henry Lee
> >
> >
> >
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