From: Chris Hansen ([email protected])
Date: Tue Dec 19 2000 - 06:56:35 PST
Aloke,
Just like building a house, building a PCB starts from the ground
up. Placement of components are going to be dictated by not only the desire
for electrical performance, but also be restricted by physical contstraints
... e.g. mounting holes in the way, you want your interface circuits close
to the IO connector but getting them all there may not be possible, shape of
the board (i.e. not square or rectangular) may not lend itself well to the
tight placement of square or rectangular IC's, etc. So certainly planning
ahead and specifying the largest board area for your application can in
general make the physical aspects of laying out the design easier. If the
ratio of your available board area (that is real board area available for
component placement) divided by the sum of the areas that the IC's in your
design will occupy (AREAboard/AREAic) equals 2, that is a pretty good
measure that your board layout and route will go pretty smoothly. If in the
early going of your design this is not the case, your placement will be a
bit more difficult, and adding more circuitry to the design later will also
be more difficult.
With that said, place the components in your design letting the
ratsnest guide your for best placement. Change interconnect, or if your
tools is capable of pin swapping, let the tool change the interconnect at
the pcb level to get the cleanest route. Layout your planes and associated
splits. Formulate the route keepouts/keepins. Route the critical signals
first (e.g. clocks, resets, strobes, and any other causal signals), then
lock them down. Then route the rest of the design, Adjust where needed,
and repeat any steps until you are sastified with the results. Depending on
the interconnect complexity of the design, several iterations may be
required.
Bottom line, I always try to get as much board area up front in the
design process. Determine the other mechanical aspects of the design, e.g.
mounting holes, area required for card guides and connectors, any special
requirements for high heat generating components, etc. so that you have a
clear picture of the real board area available for component placement and
route. Then build up the rest of the design from there. A little planning
can help in the end!
Chris Hansen
Director of Hardware Eng
StorLogic, Inc.
PH (407) 333 9998 ext. 242
FAX (407) 333 4448
[email protected]
www.storlogic.com
-----Original Message-----
From: Aloke Bhattacharya [mailto:[email protected]]
Sent: Tuesday, December 19, 2000 12:12 AM
To: [email protected]
Subject: [SI-LIST] : What first-routing/plane splitting?
Hello all,
I would like to know which one among the following two is the preferred
way of making a plane split so that we can avoid signals crossing plane
splits:
Option1: Route all signals first, and then perform the plane split.
My opinion is that this may not be a good choice because as the routing
has been done prior to plane splitting, generally signals may go left to
right/top to bottom(considering the worst case) and later on it may be
very difficult to find the optimum plane split which will avoid any
signal crossing the splits. Particularly for an autorouted board, this
may not be a good choice. Avoiding all the plane splits may require lots
of changes in the routing which may take considerable amount of time.
Option2: Do the plane splitting before starting the routing.
This looks like a good choice as we already know the location of the
splits and we can route accordingly to avoid the splits. For
autorouting, probably we can define a route keepout in the adjacent
layers wherever a split is there in the power plane( I have not tried
this keepout method yet, and I would like to get your comments on this).
I still see one more practical problem in this- when we start the
routing, generally it happens that placement is not 100% finished- and
also there are the last minuite schematic changes which adds , other
than resistors and capacitors, a few ICs also(like inverters/buffers
etc), and the earlier shape of the plane split may not be sufficient for
these new components. Now comes the problem of changing some routed nets
to avoid this new split.
So I am not able to bring a final conclusion on which one will be a
better choice.As you must have faced this problem several times in the
design phase, I would like to get your opinion on which one will be
better- routing first or splitting first or some other solution which is
better then both of the above methods.
Thanks and regards,
Aloke
-- ********************************************************************** * Aloke Bhattacharya, * * Senior Engineer-VLSI/System Design, * * * Wipro Infotech, * * Global R&D, * * 88, M.G. Road, 5th Floor, * * S.B. Towers, * * Bangalore- 560 001 , * * INDIA * * Tel : 91-80-5588422(Ext. 520) * * email: [email protected] * * ************************************************************************** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
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