[SI-LIST] : What first-routing/plane splitting?

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From: Aloke Bhattacharya (aloke.bhattacharya@wipro.com)
Date: Mon Dec 18 2000 - 21:12:04 PST


Hello all,
 I would like to know which one among the following two is the preferred
way of making a plane split so that we can avoid signals crossing plane
splits:

Option1: Route all signals first, and then perform the plane split.
 My opinion is that this may not be a good choice because as the routing
has been done prior to plane splitting, generally signals may go left to
right/top to bottom(considering the worst case) and later on it may be
very difficult to find the optimum plane split which will avoid any
signal crossing the splits. Particularly for an autorouted board, this
may not be a good choice. Avoiding all the plane splits may require lots
of changes in the routing which may take considerable amount of time.

Option2: Do the plane splitting before starting the routing.
This looks like a good choice as we already know the location of the
splits and we can route accordingly to avoid the splits. For
autorouting, probably we can define a route keepout in the adjacent
layers wherever a split is there in the power plane( I have not tried
this keepout method yet, and I would like to get your comments on this).

 I still see one more practical problem in this- when we start the
routing, generally it happens that placement is not 100% finished- and
also there are the last minuite schematic changes which adds , other
than resistors and capacitors, a few ICs also(like inverters/buffers
etc), and the earlier shape of the plane split may not be sufficient for
these new components. Now comes the problem of changing some routed nets
to avoid this new split.

So I am not able to bring a final conclusion on which one will be a
better choice.As you must have faced this problem several times in the
design phase, I would like to get your opinion on which one will be
better- routing first or splitting first or some other solution which is
better then both of the above methods.

Thanks and regards,
Aloke

--
**********************************************************************
* Aloke Bhattacharya,                                                *
* Senior Engineer-VLSI/System Design,
*                    *
* Wipro Infotech,                                                    *
* Global R&D,                                                        *
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* email: aloke.bhattacharya@wipro.com
*                                            *
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