RE: [SI-LIST] : 50 or 60 ohm impedance

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From: Moran, Brian P (brian.p.moran@intel.com)
Date: Wed Dec 13 2000 - 09:14:27 PST


Patrick,

My comment on routing density applied to a single routing layer, as oppossed
to dielectric spacing. The assumption being you have already bottomed out
on dielectric thickness, from a material handling point of view. If you can
go below 4 mils, you are correct. As far as crosstalk considerations, I am
dealing strictly with routing density through a via feild. Using a 40 mil or
50 mil BGA pin escape via feild, your routing density peaks with 3-4 mil
traces, independent of coupling rules. You can spread back out in the open
feild, but going through the array with more than a 4 mil trace cuts off
routing channels. As I said this is only my philosophy for cost effective
design.

Brian

-----Original Message-----
From: Zabinski, Patrick J. [mailto:zabinski.patrick@mayo.edu]
Sent: Tuesday, December 12, 2000 2:56 PM
To: si-list@silab.eng.sun.com
Subject: RE: [SI-LIST] : 50 or 60 ohm impedance

> One problem with using 50 ohms across the
> board is you
> often lose some routing density, if you stack up requires say
> 5 mil traces
> to get 50 ohms.

Not necessarily.

Take your favorite EM tool and simulate a pair of 50 ohm
traces at a given pitch, say 15 mils. Then, using the same
dielectric sandwich, narrow the traces a bit to obtain
60 ohms, and simulate with the same pitch (e.g., 15 mils).

What you'll see (hopefully) is that the crosstalk is less
for the 50 ohm traces than the 60 ohm traces for a given
pitch. This in turn means you can use a tighter pitch
for the 50 ohm traces than the 60 ohm traces.

Pat

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