From: Mike Saunders (firstname.lastname@example.org)
Date: Wed Dec 13 2000 - 08:37:56 PST
If you are designing not only a PCI card but also the host machine, then
you also need to route your clocks 2.5" shorter on the PCB, assuming that
you're matching the individual clock lengths. In other words, add the 2.5"
(on the card) into your total clock length figure (to the slot) when
matching to an onboard device.
At 08:55 AM 12/13/2000 -0700, you wrote:
>Thanks for the response. Being new to PCI designs I just needed verification
>of this spec.
>> -----Original Message-----
>> From: Ingraham, Andrew [SMTP:Andrew.Ingraham@compaq.com]
>> Sent: Wednesday, December 13, 2000 5:26 AM
>> To: 'Potwora, William (AZ75)'
>> Cc: 'si-list'
>> Subject: RE: [SI-LIST] : PCI CLK trace length limit
>> > Revision 2.2 of the PCI spec. paragraph 126.96.36.199 indicates that the limit
>> > is
>> > 2.5 in +/- 0.1 in.
>> > Is the 0.1in tolerance correct?
>> Yes, the +/- 0.1 inch is correct, and, in my opinion, quite reasonable.
>> 2.54 mm.
>> > Is it necessary to verify the trace length,
>> > including vias, for each design?
>> If the spec says the length must be 2.5 in +/- 0.1 in, then yes, you need
>> guarantee a length in that range for each design, whether you do it
>> or the tools do it for you. (How many designs do you have?) It should be
>> simple thing to check. Most routing tools let you do it quickly.
>**** To unsubscribe from si-list or si-list-digest: send e-mail to
>email@example.com. In the BODY of message put: UNSUBSCRIBE
>si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
>si-list archives are accessible at http://www.qsl.net/wb6tpu
**** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:26 PDT