From: Potwora, William (AZ75) (email@example.com)
Date: Tue Dec 12 2000 - 10:42:44 PST
I have a question regarding the specified PCI expansion board CLK trace
Revision 2.2 of the PCI spec. paragraph 18.104.22.168 indicates that the limit is
2.5 in +/- 0.1 in.
Is the 0.1in tolerance correct? Is it necessary to verify the trace length,
including vias, for each design?
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