RE: [SI-LIST] : layer stackup

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From: Greim, Michael (mgreim@mc.com)
Date: Tue Dec 12 2000 - 08:07:41 PST


Hi All,

Having worked on very high density cards restricted
by card guides or PCI slots, I'd like to offer some
perspective on what has worked in the past for me.
For the sake of argument I will focus my attention on
boards limited by card guide width.

Note: All of the following is covered by the global

                                I M H O

1) Are you sure that you need all those routing layers?
        Many times I have seen routing layers thrown at a
        congestion issue when in fact there may be another
        root cause, such as pad stacks incorrectly defined,
        blocking routing channels, devices off grid, incorrect
        constraints, ratnest bowtieing, etc. I would revisit
        this issue as you appear to be jumping through hoops
        (and bad ones at that) to accomodate all those signal
        layers.

2) Relieving material in the card guide area is a very common
        way (and the cheapest I dare say) of putting a thicker
        card in a thinner card guide. In the case of VME or CPCI
        a moderately thick board can be accomodated via routing the
        back side of the board. However, one must be careful doing
        this as one is impinging on back side component height. For
        a much thicker board (say .120in) a compound routing scheme
        must be employed. This gets a little trickier as one must
        route out the mechanical attach points (mounting blocks and
        connector) along with card guides to maintain proper alignement
        with the front panel. If you have any cost sensitivity
        whatever, this method is prefered to high cost thin core
        dielectrics.

3) Guarantee is a tricky word as it implies that the tool maker
        will reimburse you for your boards when the warpage is beyond
        your goals (which of course they won't). Copper fills (usually
        the method of fixing this) can only take you so far and then
        you may have some problems with impedance depending on what
        these pours are attached to. If your density is so high that
        you require so many layers, then you probably have power issues
        which means that now you will have signals on heavy weight CU
        layers (impedance issues). Remember that they copper weights
        still need to be balanced.

4) Three stripline layers smacks of a cross talk problem just
        waiting to happen. Remember that broadside coupling is stronger
        than edge, so you will need to increase your spacing to achieve
        the same coupling specs.

5) Believe it or not I have run into a PWB designer or two who
        claimed that a design could not be routed without X layers.
        We just completed a respin on a board that couldn't be routed
        in under 22 layers. With some minor massaging of the database
        it was completed in 16 and if we weren't under schedule pressure
        it could have easily been 14 or perhaps 12. Understand what
        your congestion issues are and solve them. Remember the PWB
        designer is incentivised (in many cases) to make his routing
        job as simple as possible and more layers certainly accomplishes
        this.

Just my 0.02. I hope that this helps. Do with this as ye will.

best regards and happy routing.

Michael Greim

"Making the world safe for digital signals everywhere"

-----Original Message-----
From: e [mailto:evillaf@home.com]
Sent: Tuesday, December 12, 2000 10:36 AM
To: Aric Hadav
Cc: 'si-list@silab.eng.sun.com'; 'Dave Hoover'
Subject: Re: [SI-LIST] : layer stackup

Aric,

Is it possible to add more layers to the board, and so increase the
thickness,
but keep it at 1.6 mm along the edges where it must be inserted into card
guides?

Ellis

Aric Hadav wrote:

> Hi,
>
> board thickness is fixed to 1.6 mm because of card guides.
> I thought of making a wider card and cutting it at the edges to 1.6 mm but
> that makes too many problems, hence I'm staying with 1.6mm.
> regarding the board warpage, the layout guy told me the layout software
(by
> Cadence)
> has a copper balance feature that insures a balanced board by the end of
the
> layout.
> still, I'm not confident with that.
> has anyone has a better stackup in 1.6 mm ? or other ideas ?
>
> thanks,
> Aric
>
> -----Original Message-----
> From: Dave Hoover [mailto:dave_hoover@yahoo.com]
> Sent: Tuesday, December 12, 2000 4:08 AM
> To: Aric Hadav; 'si-list@silab.eng.sun.com'
> Subject: Re: [SI-LIST] : layer stackup
>
> Aric,
> 14 layers in 1.6 mm is tough but possible. It looks
> like your forced to go this way based on necessary
> signal layers. Unfortunately this stackup you've
> proposed is not well balanced. There may be a
> considerate amount of warpage because of this
> unbalanced stackup. Being 1.6mm thk just compounds
> the warpage. Is there any way to add redundant
> planes (to balance the stackup) and increase the
> overall thickness? (Is the thickness locked in due
> to card guides, pressfit pin lengths, or something?)
>
> Dave Hoover (fab guy learning about SI)
>
> --- Aric Hadav <Aric@accord.co.il> wrote:
> > Hi,
> >
> > I'm looking for some help on deciding on my board
> > layer stackup.
> > my design has ~20K pads and it must fit into a
> > standard 6U board, 1.6 mm
> > thick.
> > the board thickness CAN NOT be changed.
> >
> > the PCB layout guy told me that the design can only
> > fit into a minimum of 14
> > layers stack up,
> > with a 3-4 mil core and preg thickness, as described
> > below:
> > 1. CS
> > 2. sig1
> > 3. VCC1V8
> > 4. sig2
> > 5. sig3 (ctrl impedance).
> > 6. sig4
> > 7. GND
> > 8. sig5
> > 9. sig6 (ctrl impedance).
> > 10. sig7
> > 11. VCC3V
> > 12. sig8
> > 13. sig9
> > 14. PS
> >
> > now, this looks some what strange to me since layers
> > 5 & 9 aren't adjacent
> > to a PWR/GND
> > plane, since one should always try that a signal
> > layer will be close to
> > reference plane.
> > now, in order to reduce the crosstalk between layers
> > 4 to 6 or 8 to 10 he
> > suggested to route the
> > signals not horizontally and vertically but
> > layers 4, 8 - 45 degrees.
> > layers 5, 9 - vertical or horizontal.
> > layers 6, 10 - 135 degrees.
> > has anyone routed this way ? did it work ok ?
> > the signal clocks will be routed in layers 5 and 9
> > which supposed to be
> > control impedance. is it ok ?
> > has anyone has other suggestions to the layer
> > stuckup?
> >
> > thanks,
> >
> > Aric Hadav
> > Hardware Design Engineer
> > aric@accord.co.il
> >
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