From: e (firstname.lastname@example.org)
Date: Tue Dec 12 2000 - 07:36:01 PST
Is it possible to add more layers to the board, and so increase the thickness,
but keep it at 1.6 mm along the edges where it must be inserted into card
Aric Hadav wrote:
> board thickness is fixed to 1.6 mm because of card guides.
> I thought of making a wider card and cutting it at the edges to 1.6 mm but
> that makes too many problems, hence I'm staying with 1.6mm.
> regarding the board warpage, the layout guy told me the layout software (by
> has a copper balance feature that insures a balanced board by the end of the
> still, I'm not confident with that.
> has anyone has a better stackup in 1.6 mm ? or other ideas ?
> -----Original Message-----
> From: Dave Hoover [mailto:email@example.com]
> Sent: Tuesday, December 12, 2000 4:08 AM
> To: Aric Hadav; 'firstname.lastname@example.org'
> Subject: Re: [SI-LIST] : layer stackup
> 14 layers in 1.6 mm is tough but possible. It looks
> like your forced to go this way based on necessary
> signal layers. Unfortunately this stackup you've
> proposed is not well balanced. There may be a
> considerate amount of warpage because of this
> unbalanced stackup. Being 1.6mm thk just compounds
> the warpage. Is there any way to add redundant
> planes (to balance the stackup) and increase the
> overall thickness? (Is the thickness locked in due
> to card guides, pressfit pin lengths, or something?)
> Dave Hoover (fab guy learning about SI)
> --- Aric Hadav <Aric@accord.co.il> wrote:
> > Hi,
> > I'm looking for some help on deciding on my board
> > layer stackup.
> > my design has ~20K pads and it must fit into a
> > standard 6U board, 1.6 mm
> > thick.
> > the board thickness CAN NOT be changed.
> > the PCB layout guy told me that the design can only
> > fit into a minimum of 14
> > layers stack up,
> > with a 3-4 mil core and preg thickness, as described
> > below:
> > 1. CS
> > 2. sig1
> > 3. VCC1V8
> > 4. sig2
> > 5. sig3 (ctrl impedance).
> > 6. sig4
> > 7. GND
> > 8. sig5
> > 9. sig6 (ctrl impedance).
> > 10. sig7
> > 11. VCC3V
> > 12. sig8
> > 13. sig9
> > 14. PS
> > now, this looks some what strange to me since layers
> > 5 & 9 aren't adjacent
> > to a PWR/GND
> > plane, since one should always try that a signal
> > layer will be close to
> > reference plane.
> > now, in order to reduce the crosstalk between layers
> > 4 to 6 or 8 to 10 he
> > suggested to route the
> > signals not horizontally and vertically but
> > layers 4, 8 - 45 degrees.
> > layers 5, 9 - vertical or horizontal.
> > layers 6, 10 - 135 degrees.
> > has anyone routed this way ? did it work ok ?
> > the signal clocks will be routed in layers 5 and 9
> > which supposed to be
> > control impedance. is it ok ?
> > has anyone has other suggestions to the layer
> > stuckup?
> > thanks,
> > Aric Hadav
> > Hardware Design Engineer
> > email@example.com
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