From: Zabinski, Patrick J. (firstname.lastname@example.org)
Date: Mon Dec 11 2000 - 04:42:50 PST
I have not analyzed/utilzed triple-stripline as you have shown,
but I have analyzed quad-stripline. i.e.,
sig-S (45 degrees)
sig-X (0 degrees)
sig-Y (90 degrees)
sig-T (-45 degrees)
Here, all four layers were controlled impedance at roughly 50 ohms.
For our system, the data rate was around 100-150 Mbps with edge
rates slightly below 1 nsec.
We ran a series of eye diagram simulations and built a few
passive test boards, and the end result was that we were confident
enough in our results to go forward in using the quad stripline.
That said, I personally believe we were nearing the edge of
performance. We did not have sufficient time to come to a
final/firm determination, but my personal engineering-guess
is that the quad-stripline (in the configuration we were using)
had an upper limit around 200 Mbps. Above this, the eyes
were closing too much in both time and amplitude.
> I'm looking for some help on deciding on my board layer stackup.
> my design has ~20K pads and it must fit into a standard 6U
> board, 1.6 mm
> the board thickness CAN NOT be changed.
> the PCB layout guy told me that the design can only fit into
> a minimum of 14
> layers stack up,
> with a 3-4 mil core and preg thickness, as described below:
> 1. CS
> 2. sig1
> 3. VCC1V8
> 4. sig2
> 5. sig3 (ctrl impedance).
> 6. sig4
> 7. GND
> 8. sig5
> 9. sig6 (ctrl impedance).
> 10. sig7
> 11. VCC3V
> 12. sig8
> 13. sig9
> 14. PS
> now, this looks some what strange to me since layers 5 & 9
> aren't adjacent
> to a PWR/GND
> plane, since one should always try that a signal layer will
> be close to
> reference plane.
> now, in order to reduce the crosstalk between layers 4 to 6
> or 8 to 10 he
> suggested to route the
> signals not horizontally and vertically but
> layers 4, 8 - 45 degrees.
> layers 5, 9 - vertical or horizontal.
> layers 6, 10 - 135 degrees.
> has anyone routed this way ? did it work ok ?
> the signal clocks will be routed in layers 5 and 9 which
> supposed to be
> control impedance. is it ok ?
> has anyone has other suggestions to the layer stuckup?
> Aric Hadav
> Hardware Design Engineer
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