[SI-LIST] : Controlling switching noise in full-swing CMOS buffers (was Despite output resistor to reduce overshoot and undershoot)

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From: Zabinski, Patrick J. (zabinski.patrick@mayo.edu)
Date: Wed Dec 06 2000 - 04:40:26 PST


If you have the ability to influence the pre-drive stage,
then I'm assuming you're designing your own buffer. If
this is the case, there are a few things you should
definitely consider.

#1) Higher impedance: The vast majority if switching noise in
an output buffer is from the final output stage. Considering
the voltage noise is delta-V = L * di/dt, sometimes the easiest
way of reducing delta-V is to reduce di. di in is related to
the output impedance. If you can increase the output impedance,
you will reduce di, which in turn will lower delta-V (noise).
This is accommplished by reducing the size of the final driver
transistors. Two important issues to keep in mind:

        * maintain the same output impedance for both rising
          and falling edges
        * SIMULATE(!) the buffer driving a representative
          load to ensure you did not take this too far, or
          you could end up with overwelming undershoot.

#2) Edge rate control: Similarly, you can also reduce
delta-V = L * di/dt by increasing dt. This is accomplished
in the pre-drive stage. The final drive transistors will
toggle stages per the voltage at their gates. By slowing
down the gate control voltages, you'll slow down the
output edge rate. To slow down the control voltage,
simply under-size the predrive transistors.

Caution: If done incorrectly, you can end up with tremendous
crowbar current and actually increase delta-V.

To avoid it, you must:

        * undersize the NMOS of the predrive stage that
          controls the final PMOS drive transistor (i.e.,
          controls rising edge) while keeping the mating
          PMOS of the same predrive stage the normal size

        * undersize the PMOS of the predrive stage that
          controls the final NMOS drive transistor (i.e.,
          controls falling edge) while keeping the mating
          NMOS of the same predrive stage the normal size

Also, do not slow the buffer down to the point where you
have eaten away all your timing margin.

#3) Lower inductance: Back to the same old equation, delta-V
= di/dt; try to reduce L with wide power busses, short
wire bonds, etc.

#4) On-chip decoupling: You can play a lot of tricks with
buffers, but regardless of what you do, the buffer will always
have some level of demand for switching currents. Traditionally,
the switching currents were supplied off-chip. However, if
you have the real estate on-chip, you can insert a small
on-chip capacitor cell between VDD and VSS right next to every
buffer (make it part of the buffer cell, if you can).

Caution: Too high of capacitance so close to the bond wires
can result in resonances. Again, SIMULATE the buffer driving
an appropriate load taking into accound the VDD and VSS
parasitics to make sure you did not take it too far.

As a starting point, I like to get 25-75 pF per buffer in
typical full-swing CMOS buffers with nominal 50 ohm
output impedance.

#5) Linear output impedance: The end goal is not necessarily
to reduce noise, but is to improve signal integrity. To
do this, you might consider some form of linearizing circuit
on the final output stage. Most generic buffer designs
have simple PMOS-NMOS ladders as the final stage, and
their respective output impedances vary dramatically depending
upon the output voltage (governed by the I-V curves).
There are a few ways to linearize the output impedance such
that it stays relatively flat over the bulk of the output
voltage range. Sorry I cannot share circuits with you
(proprietary to others or me), but if you have the time,
it's worth looking into.

In short, there are a few design tricks you can play that
can improve your switching noise by significant amounts (50-80%).
(there are probably more than just these as well)
However, each "trick" can be taken too far or done incorrectly,
which in turn could make it worse. If this is your first time
dealing with these issues, make sure you either have
an experienced person helping/reviewing and/or test your design
with a breakout macro on a test chip before you commit to
final silicon.

Hope this helps,

> Hi
> Despite the fact that I can use resistor to reduce output noise,
> are there other novel ways such that I need not compensate the
> output level while still can reduce noice, Or can I do sth in the
> pre-drive stage before the output stage ?
> Thanks alot
> Kenneth

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