RE: [SI-LIST] : Clock Termination (WAS: Why can a resistor can re duce noise in output buffer)

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From: Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Date: Sun Dec 03 2000 - 15:26:05 PST


> > Do not use this type of termination for clocks if you have more than one
> > clock receiver on line; series termination for clocks is only good for
> > point-to-point connection.
> Why?
 
Assuming that you routed serially from the driver to all receivers
("daisy-chain" from one to the next), the problem is that each receiver
except the last one sees the half-amplitude signal for a short time. Thus,
there is a nice glitch or plateau, right in the middle of each edge. For a
clock or clock-like signal, this can be disastrous, causing double-clocking
to occur at some receivers. Only the receiver on the far end sees clean
edges.

If you routed some other way, for example, separate traces from the driver
to each receiver, then you need to be careful exactly how you handle it.
Using a single "series termination" resistor (keeping in mind the fact that
the effective trace impedance for N traces is Zo/N) might not work,
especially if the trace lengths are unequal.

Any time there's a clock, you need to be careful. Most non-clock signals
will forgive many "sins", because they are "observed" only for a brief
moment each cycle. Not so with clocks.

If you don't have the tools to simulate them, it's best not to try doing
short-cuts such as routing one line to multiple clock loads.

Regards,
Andy

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