[SI-LIST] : FPGA IBIS model

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From: KokTongTHAM (kt_tham@uti2000.co.jp)
Date: Wed Nov 22 2000 - 14:02:33 PST


Dear SI gurus,

I have an interconnect between Virtex FPGA(Xilinx) and SDRAM(Hitachi).
When Data read back from SDRAM, the waveform contain a lot of terrible
ringing and overshoot.
I have doubt about the [Power Clamp] in FPGA(I/O model) to have any
effect
at all.

Can anybody give me any comments and solutions regarding the models?
(see attachment files)

Regards,
KTTHAM

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