From: e ([email protected])
Date: Tue Nov 21 2000 - 23:13:49 PST
I am working on an 8-port 10/100 ethernet board plagued with what seems
to be noise problems.
When running in 10 Mbps mode, all ports are error free. But when
running in 100 Mbps mode, some ports occassionally take error hits
mostly in the transmit direction (about 2 packets out of 10 million),
but one port in particular experiences CRC errors in the receive
direction in the order of 20 packets per 10 million sent.
I am using 2 Level One LXT974 phy devices and followed Level One board
layout recommendations per Level One AN84 with the following added:
1) Traces from RJ-45 connector to magnetics are shielded with frame
ground for EMI control. Frame ground shielding is at least 3 layers
away to reduce parasitic capacitance between the frame ground plane and
2) In addition to power plane partitioning, ground planes are also
similarly partitioned: analog ground below analog VCC, etc, with clean
25 mil isolation between them that run the thickness of the board.
Analog ground is tied to digital ground at one point with a 3A ferrite
bead. The same ferrite bead is used on the power planes. Lots of bulk
caps and 0.1uF caps are used.
3) The split termination with two 50 ohm resistors connected to form
100 ohm termination, and a common-mode bypass cap in the middle is used
on receive ports.
I am running out of ideas on where the CRC problems could be coming
from, especially the one in the receive direction.
I have done some return loss measurements with a balun and a network
analyzer and found the return loss exceeds that required by the
I have used an oscilloscope with a balanced probe to look at the
problematic receive port and didn't find any noticeable differences
compared to a consistently working receive port.
I have tried using a single 100 ohm resistor for termination and found
no change in
I have improved on the current layout with the following:
1) the 22k ohm bias resistor is placed next the the Phy pin connection.
2) bypass caps are also next to power/ground pins.
3) power and ground traces and minized
4) analog trace width is increased from 8 mil to 12 mil (will this
Any suggestions would be appreciated. In particular, I would like to
know if there are recommended layout practices in the area between the
RJ-45 connectors and the phy devices. Is there a trace width
requirement, or trace spacing recommendations between the differential
pairs in the region between the RJ-45 connectors and the magnetics,
where no reference ground is used (voided to keep power and ground plane
noise away from traces leaving the chassis)?
Thanks in advance,
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