RE: [SI-LIST] : PCI Bus problem (an interesting one)

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From: Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Date: Mon Nov 20 2000 - 21:37:44 PST


In general you should start with best- and worst-case models. Then as long
as the models are good, your sims will bracket what you will see in the lab.
Hopefully the best- and worst-case models are not so far apart that you
could get anything.

But the key thing, always, is having models you can trust and believe.
Without that, there's no point to running SPICE, it will tell you nothing.

On the other hand, you should not expect lab measurements to match
simulations. Nor should you expect a vendor to sell you ICs whose
characteristics are always the same! Nobody is going to mass-produce an IC
that behaves exactly like a single (i.e., typical) SPICE model; so you
shouldn't expect it. They WILL change, it is a fact of life. Your lab
measurements should fall within the best- and worst-case simulations. Don't
throw out the simulations just because the measured data wasn't the same.
Over the lifetime of your product, your vendors' processes will shift and
you might see parts at one or both corners.

There is not necessarily anything wrong with seeing 4ns in the lab vs. 1.3ns
in best-case simulations; but if your worst-case sims also show faster
edges, then something is wrong.

Putting 180pF on a driver's output was simply a technique you used to
artificially slow down a driver; but don't use it as "proof" that the
vendor's model was off by that much. There are other ways of slowing a
driver that use far less capacitance, in different places. The driver might
be relatively unaffected by capacitive loading over a wide range, so you had
to go way up to 180pF to see enough effect to do what you wanted. Maybe the
model correctly shows how a best-case driver really behaves.

I am puzzled why the simulation results changed so dramatically when you
re-did them. Find out why! Go back to the original models and change
things one at a time until you determine what made them change so much.

Maybe you have an interaction between the models that is making one of them
behave wrong. For example, if any of the models uses a global .OPTION SCALE
or SCALM factor, that would render your simulations useless.

Or as Scott McMorrow pointed out, be careful with the IBIS model in HSPICE,
because it is easy to hook it up wrong so that its clamps don't work.

In addition to the one with the IBIS model, make sure there is a package
model for each of the other devices.

Are only the overshoot magnitudes wrong, or are the widths of any of the
pulses very different from what you see in the lab? If the traces got
entered wrong in your simulations (perhaps as mils rather than inches), you
could see some disastrous results.

Mike Nudelman suggested adding series resistors at the drivers, and doubling
up the IC pins. You might do fine with just the resistors (10-30 ohm range)
and not doubling up the IC pins; the extra delay through small resistors to
the inputs ought to be small. Series resistors are a good remedy if the
drivers are too "hot", especially for PCI.

> I hadn't read through the whole thing yet, but PCI is not exactly
> unterminated.
> It uses whimpy drivers with high output Z, which serves as a series
> termination,
> so when your voltage doubles at the end due to open load, the signal
> becomes
> normal height, without much over/under-shooting.

Wimpy drivers? Many would argue with that. Series terminated? Ideally,
yes. In practice, not very well. PCI tends to be somewhat
under-terminated, so in some cases there can be significant overshoot.

Anyway, the range between min and max drive strength can be so great (10:1)
that there's little chance of truly matching the driver impedance over all
variations.

The other important termination would be the clamp diodes built into every
PCI device. You can get overshoot, but the diodes clamp and absorb some of
the excess energy.

> - only looking at typ simulation data (real board may be closer to
> min or max)

Often it's the other way around; devices are near typical but models are
best- and worst-case. It's the "safe" way to do it, but may give you
heartburn until you sample enough real boards to realize you're not that
bad.

> - limited bandwidth of scope used to measure board or poor
> connection to board.

The overshoots on PCI can last several nanoseconds, long enough so that even
less-than-top-bandwidth scopes with non-ideal probes would show it.

Andy

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