Re: [SI-LIST] : PCI Bus problem (an interesting one)

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From: Scott McMorrow (scott@vasthorizons.com)
Date: Mon Nov 20 2000 - 19:15:14 PST


Bo,

First, you should make measurements at the driver pins
themselves to determine if they come close to matching
one of the corners of the model being simulated. To check
for this, you will need to try and determine the output
impedance of the driver and it's launched slew rate.

Measurement 1 is to TDR the board to determine the
characteristic impedance of the traces.

Measurement 2 would be to measure the launched
rising edge of the driver at the pin of the Xilinx device.
(It is easiest to measure accurately, since it is at the
end of the bus and has a 3inch trace between it and
the next discontinuity.) The voltage of the first "ledge"
in the waveform can be used to compute the output
impedance of the driver. (since you know the characteristic
impedance of the bus from Measurement 1, this is
straight forward). Then you can measure the 20-80%
rise time, with the 100% point being the first ledge itself.

These measurements allow you to go into the ibis model
and determine if it is reasonably correct. To get a
rough guesstimate of the output impedance of an IBIS
model for the Pullup, look up the current at 1V in the
table. The output impedance is 1V divided by this
current. (You can do the same for all corners and for
the pulldown curves, also.)

For a correctly constructed IBIS model, the dT section
of the ramp data will give you the range of edge rates
that can be seen from min to max corners. You can
compare this directly to the physical measurement
that you made.

If your measurements are within reasonable range
of the IBIS model, then you are good to go.
If not, you have either a bad measurement, or a
bad model.

Please be sure to check your measurement and
probing techniques. You will need a scope with
a bandwidth greater than 1 Ghz and probes with
greater than 1 GHz bandwidth to make accurate
measurements of the edgerates, along with
overshoot and undershoot.

If the Xilinx model correlates fairly well on the
rising edge (up to the ledge) with the model, then
the problem is elsewhere in the modeling. At this
point it most likely has something to do with
package modeling, clamp, or die capacitance
modeling.

Be aware, HSpice does not model IBIS packages.
You must add the package model as a seperate
circuit. (This is the first possible source of error.)

Second, if you are modeling I/O buffers in HSpice
it is easy to not enable the clamps. Even if you
do not use these nodes in the circuit, you must
include the pc and gc nodes in the B-element
model call, to cause the clamps to be enabled.
Otherwise, the clamp curve is added to the output
pullup and pulldown curves, and is not used
for input modeling. (This is the other possible
error that you could be having ... and is likely,
since you are showing huge overshoot and
undershoot values in simulation. PCI clamps
are huge by design and by specification. You
should not see such large excursions in simulation,
unless the clamps are not active.)

Best regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

Bo wrote:

> Thanks for the reply Mike. > > I agree with everything you said. I am doubting the models. I also know that > terminations should not be done on PCI bus (unless you are using ring topology > and even then only after carefull consideration). What I am seeing in the lab > is very very slow compared to what I see in simulations. If I can get > guarantee that I/O buffers would be slow all the time I would be very happy. > But I can't. The measurments may not be correct, but I am almost sure that > this is not the case. > > Regards, > Bo > > --- Mike Mayer <mwmayer@tds.net> wrote: > > [PCI problems simulation vs. real board] > > > > PCI is meant to be unterminated and so there can be overshoot and > > ringing. That said, I can think of several things that can cause > > differences between simulated and measured results: > > > > - models (of course) > > - only looking at typ simulation data (real board may be closer to > > min or max) > > - limited bandwidth of scope used to measure board or poor > > connection to board. > > > > -- > > ============================================================================= > > Mike Mayer > > mwmayer@tds.net > > > > > > __________________________________________________ > Do You Yahoo!? > Yahoo! Calendar - Get organized for the holidays! > http://calendar.yahoo.com/ > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

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