Re: [SI-LIST] : PCI Bus problem (an interesting one)

About this list Date view Thread view Subject view Author view

From: Bo (bo_pfc@yahoo.com)
Date: Mon Nov 20 2000 - 12:41:24 PST


Thanks for the reply Mike.

I agree with everything you said. I am doubting the models. I also know that
terminations should not be done on PCI bus (unless you are using ring topology
and even then only after carefull consideration). What I am seeing in the lab
is very very slow compared to what I see in simulations. If I can get
guarantee that I/O buffers would be slow all the time I would be very happy.
But I can't. The measurments may not be correct, but I am almost sure that
this is not the case.

Regards,
Bo

--- Mike Mayer <mwmayer@tds.net> wrote:
> [PCI problems simulation vs. real board]
>
> PCI is meant to be unterminated and so there can be overshoot and
> ringing. That said, I can think of several things that can cause
> differences between simulated and measured results:
>
> - models (of course)
> - only looking at typ simulation data (real board may be closer to
> min or max)
> - limited bandwidth of scope used to measure board or poor
> connection to board.
>
> --
> =============================================================================
> Mike Mayer
> mwmayer@tds.net
>
>

__________________________________________________
Do You Yahoo!?
Yahoo! Calendar - Get organized for the holidays!
http://calendar.yahoo.com/

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:11 PDT