RE: [SI-LIST] : matched delay

About this list Date view Thread view Subject view Author view

From: Charles Hill (
Date: Mon Nov 20 2000 - 11:33:15 PST


It seems we may be in agreement here. I'm saying that both timing skew
between positive and negative differential inputs and impedance mismatches
are linear processes. Therefore, they cannot produce duty cycle distortion.

The transmission channel in question is the differential mode channel from
transmitter to receiver. A differential mode receiver produces an output
according to vout = vpos - vneg, a linear equation. The transmission
channel is also linear.

It seems that distortions like "wiggles and bends" or "asymmetric edges"
could be caused by entirely linear processes in the channel, and if the
differential receiver conforms to vout = vpos - vneg, then no duty cycle
distortion results. On the other hand if duty cycle distortion does
result, then the receiver input must be partially non-linear to the
differential mode input signal. For example, if the differential receiver
inputs go to an input level where the equation changes (like the gain
changes), then it has non-linearity.

If the timing skew between positive and negative sides of the differential
mode input goes beyond the rise and fall times, then the differential mode
signal has regions near zero and flat. Then the finite gain and noise of
the differential receiver produce large uncertainties in the timing of the
logic edge.

I think that's pretty much what you said. I'm interested in any other
insights you may have. Like what causes this duty cycle distortion in the

Chuck Hill

At 01:18 PM 11/20/00 -0500, Ingraham, Andrew wrote:
>I don't know precisely how it might cause duty cycle distortion either ...
>however, your analysis is too narrow because it doesn't include the
>unavoidable effects of the driver and receiver.
>For example, if the driven waveforms have some anomalies; like wiggles or
>bends somewhat away from the 50% points, which might be caused by the
>nonlinear behavior of the driver; or asymmetrical edges on the true and
>complement signals; then unequal delays might shift the signal crossings to
>points you are better off avoiding.
>The transmission line does not create even order harmonics, but the receiver
>can, when it slices the differential input and squares it up. If the
>differential input level at the signal crossing point decreases enough, it
>could influence the (imperfect) receiver to have asymmetrical delays. If
>the delay mismatch is bad enough that the differential signal at the
>receiver falls to zero for a short (non-zero) time, then all bets are off.
>Very small offsets could lead to significant time differences between
>leading and trailing edges.
> > ----------
> > You said that mismatches cause duty cycle distortion. I don't understand
> > the causal relationship. My reasoning goes as follows:
> > Mismatches and reflections occur in transmission channels which are linear
> > time invariant. A property of linear systems is no additional frequency
> > components are created (intermodulation does not occur). For example, if
> > a perfect square wave goes through a linear channel, only odd order
> > harmonics go in and come out. Now duty cycle distortion implies even
> > order harmonics are produced by a transmission channel with a perfect
> > square wave input. But this is a contradiction since mismatches are a
> > linear process which do not produce additional frequency components.
> >
> > The linear transmission channel affects positive and negative edges the
> > same. These channels are characterized by an impulse response.
> >
> > That what it looks like to me. What do you think?
> >

**** To unsubscribe from si-list or si-list-digest: send e-mail to In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:11 PDT