RE: [SI-LIST] : matched delay

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From: Larry Miller (ldmiller@nortelnetworks.com)
Date: Mon Nov 20 2000 - 07:42:58 PST


As others have or will point out, mismatches cause loss of input level. They
also cause duty cycle distortion (DCD), in my opinion. The practical result
of this is that EMI is increased because the electromagnetic fields of the P
and N signals cannot scrinch down and cancel.

Remembering that LVDS was originally designed as a cable link technology,
you might take some guidelines from similar speed wire standards.

For example, 100BASE-TX (which is actually 125 MHz, close enough to 155) the
allowable DCD is 1/16 of a Unit Interval (0.5 ns out of 8 ns). Obviously,
this gets tougher as you increase in frequency, but you probably ought to
try for less than 50 ps.

My $.02

Larry Miller

> -----Original Message-----
> From: Khanh Le [SMTP:bastilles@yahoo.com]
> Sent: Monday, November 20, 2000 4:55 AM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : matched delay
>
> Hi,
>
> I am new to this forum and have an issue with the PCB
> layout of differential pair signals such LVPECL, LVDS
> and CML. Are there any rule of thumb for matched delay
> ? e.g. what should be the maximum difference in trace
> length between the p and n of the differential pair,
> where the signal is still considered to be within the
> safe margin. I have signals running at 155MHz, 622MHz,
> 1.25GHz and 2.5GHz. Thank you all.
>
> Khanh
>
>
>
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