Re: [SI-LIST] : matched delay

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From: Michael Nudelman (mnudelman@tellium.com)
Date: Mon Nov 20 2000 - 06:34:59 PST


Khanh:

Rough estimate: calculate all your desired additional signal loss
margin, left after you added up all known skew sources, losses for skin
effect, trace impedance, cables etc. Then take your skew number, which
is roughly 6 inches per ns, or 6 mils per ps. So, every, say, 20 mils
traces' skew will give you 120 ps signal skew. Knowing your slopes'
worst case slew rate and the worst case diff. amplitude, rougly
estimate, what percentage of the amplitude you will loose, and see, if
it still within your receiver's worst case tolerance for minimum signal.

The skew itself will not directly add to jitter, but, as you can see,
will add to losses

Khanh Le wrote:

> Hi,
>
> I am new to this forum and have an issue with the PCB
> layout of differential pair signals such LVPECL, LVDS
> and CML. Are there any rule of thumb for matched delay
> ? e.g. what should be the maximum difference in trace
> length between the p and n of the differential pair,
> where the signal is still considered to be within the
> safe margin. I have signals running at 155MHz, 622MHz,
> 1.25GHz and 2.5GHz. Thank you all.
>
> Khanh
>
>
>
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