From: Khanh Le (firstname.lastname@example.org)
Date: Mon Nov 20 2000 - 04:54:40 PST
I am new to this forum and have an issue with the PCB
layout of differential pair signals such LVPECL, LVDS
and CML. Are there any rule of thumb for matched delay
? e.g. what should be the maximum difference in trace
length between the p and n of the differential pair,
where the signal is still considered to be within the
safe margin. I have signals running at 155MHz, 622MHz,
1.25GHz and 2.5GHz. Thank you all.
Do You Yahoo!?
Yahoo! Calendar - Get organized for the holidays!
**** To unsubscribe from si-list or si-list-digest: send e-mail to
email@example.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:10 PDT