From: Khanh Le (email@example.com)
Date: Mon Nov 20 2000 - 04:54:40 PST
I am new to this forum and have an issue with the PCB
layout of differential pair signals such LVPECL, LVDS
and CML. Are there any rule of thumb for matched delay
? e.g. what should be the maximum difference in trace
length between the p and n of the differential pair,
where the signal is still considered to be within the
safe margin. I have signals running at 155MHz, 622MHz,
1.25GHz and 2.5GHz. Thank you all.
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