RE: [SI-LIST] : deCoupling caps and there placement

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From: Larry Smith ([email protected])
Date: Tue Nov 14 2000 - 11:03:18 PST

I don't believe you can make any strong statements about the power
plane dielectric thickness and effective location of decoupling
capacitors. It is very product dependent. The power plane and
decoupling capacitor configuration required for a 100 watt product is
very different than that required for a 10 watt product.

The impedance of the power distribution system for the 100 watt product
must be 1/10th that of the 10 watt product. Ten times the current will
be required assuming a 5% voltage tolerance on the same supply voltage
for each product. For example, a 2 volt 10 watt product requires 5
amps and a 2 volt 100 watt product requires 50 amps. The target
impedance for the 10 watt product is 5%*2V/5amps = 20 mOhms and the
target impedance of the 100 watt product is 2 mOhms.

At high frequencies (beyond the bandwidth of the regulator), that
impedance comes from decoupling capacitors and power planes. Ceramic
decoupling capacitors have the characteristic "V" in the impedance vs
frequency curve, with the bottom of the "V" being the capacitor ESR.
You must place enough capacitors in parallel such the combination of
all the ESR's in parallel reaches the target impedance across a broad
frequency range, up to the frequency where you no longer care (ie 100
MHz or more). Ref 1 is a paper that tells how to do this.

Once we have chosen a selection of capacitors that meet the target
impedance across the broad frequency range, we have to connect those
capacitors to the circuit (i.e. uP) that consumes the power. That is
done with power planes. Obviously, the impedance of the power planes
must be less than the impedance of the parallel capacitors, or else
there will be so much voltage drop across the power plane impedance
that the low impedance capacitors will not be of any service. For a
particular product, 10 mil separation in power planes may be sufficient
and 30 mils may not be sufficient. The product requirements depend on
the target impedance and power consumption of the product.

Consider the following table of power plane properties as a function of
dielectric thickness:

parameter 4mil 10mil 30mil units
---------------------- ------ ------ ------ ------
capacitance per area: 225 90 30 pF/square_inch
spreading inductance: 0.13 0.32 0.96 nH/square
power plane impedance: 0.75 1.87 5.6 Ohm-inch

The spreading inductance is a property of the material and comes in
units of henries/square (similar to ohms/square for spreading
resistance). The power plane impedance comes in Ohm-inch. A long, 1
inch wide strip of the material has Z0= 0.75 Ohms in the case of 4 mil
material. More details on this discussion can be found in ref 2.

From the above table, it can be seen that the capacitance is
proportional to, and the inductance and impedance are inversely
proportional to the thickness of the dielectric. The power planes must
have sufficiently thin dielectric so that they do not become the
dominant impedance between the decoupling capacitors and the power
consumers. At Sun, we frequently use 2 mil thick dielectric, and
possibly multiple layers in parallel to achieve a power plane impedance
that is small compared to the capacitors attached to it. We use the
power planes described in ref 2 for spice analysis of capacitors
mounted on the planes to see if we have provided sufficient energy
(voltage and current) to the chips that consume the power.

One more comment on the placement of decoupling capacitors: at low
frequency, position on the pcb does not matter. At high frequencies,
cavity resonance's develop on the PCB. The position of a capacitor on
the PCB becomes very important if the resonant frequency of that
capacitor is above the 1/4 wavelength frequency of the PCB. Take for
example a capacitor that resonates at 500 MHz, period = 2nSec. A
quarter wavelength is 0.5 nSec or 3 inches in FR4. If you put an
impedance minimum (@500MHz) 3 inches from a power consumer, it will
appear to to be an impedance maximum! Position is very important for
this capacitor.

Ref 1: Larry Smith, Raymond Anderson, Doug Forehand, Tom Pelc, Tanmoy
"Power Distribution System Design Methodology and Capacitor Selection
for Modern
CMOS Technology," Transactions on Advanced Packaging August, 1999 pp

Ref 2: Larry Smith, Raymond Anderson, Tanmoy Roy, "Power Plane Spice
Models for Frequency and Time Domains," Electrical Performance of
Electronic Packages conference, Oct 2000.

Larry Smith
Sun Microsystems

> Delivered-To: [email protected]@fixme
> X-Sender: [email protected]
> Date: Mon, 13 Nov 2000 16:36:34 -0800
> To: "Ken Cantrell" <[email protected]>, [email protected]
> From: Doug Brooks <[email protected]>
> Subject: RE: [SI-LIST] : deCoupling caps and there placement
> Mime-Version: 1.0
> I interpret it just as it says and as Todd says in the interview.
> The study that said "the location of the decoupling ...unimportant" (which
> study is referenced in footnote 4 and which study is the oft quoted Tod
> Hubing, et al study of 1995) applied only to narrowly spaced planes (10
> mils), and not to other configurations. Therefore, the "unqualified"
> extension to the idea that placement in unimportant (in general) is
> projecting beyond the validity of the study. The paper in 1995 simply does
> not show that placement is unimportant in the general case --- only in the
> case where the planes are closely spaced (within 10 mils.)
> Doug
> At 03:57 PM 11/13/00 -0700, you wrote:
> >Mark & Doug,
> >How do you interpret that?
> >Ken
> >-----Original Message-----
> >From: [email protected]
> >[mailto:[email protected]]On Behalf Of Mark Gill
> >Sent: Monday, November 13, 2000 11:16 AM
> >To: 'Doug Brooks'; Thomas Jackson; [email protected]
> >Subject: RE: [SI-LIST] : deCoupling caps and there placement
> >
> >Folks - Just a note on the UMR work. To quote a UMR sponsored paper for
> >the 2000 EMC symposium, "Quantifying Decoupling Capacitor Location", the
> >paper states,
> >
> >"A more recently published study of decoupling capacitors and printed
> >circuit boards as ensembles concluded that for printed circuit boards with
> >both power and ground planes, all decoupling capacitors are shared in the
> >frequency range in which they are effective; hence, the location of the
> >decoupling capacitor on the board is unimportant [4]. This study
> >considered multi-layer boards with closely spaced layers and its
> >conclusions may have been extended beyond the region of validity of the study."
> >
> >[4] T. Hubing, J. Drewniak, T. Van Doren, and D. Hockanson, "Power Bus
> >Decoupling on Multilayer Printed Circuit Boards," IEEE Transactions on
> >Electromagnetic Compatibility, Vol. 37, No. 2, pp. 155-166, May 1995.
> >
> >Regards,
> >
> >Mark Gill, P.E.
> >EMC/Safety/NEBS Design & Compliance
> >C-MAC Engineering Design Services
> >
> >-----Original Message-----
> >From: Doug Brooks [<mailto:[email protected]>mailto:[email protected]]
> >Sent: Monday, November 13, 2000 12:23 PM
> >To: Thomas Jackson; [email protected]
> >Subject: RE: [SI-LIST] : deCoupling caps and there placement
> >
> >But, I too would call your attention to an article that appeared in PC
> >Design Magazine in March, 1998 titled "An Interview With Todd Hubing" (a
> >reprint is available in the "articles" section of our web site at
> ><> Todd qualified the
> >comments in the article you
> >referenced as applying only to boards where the power planes were 10 mils
> >or less apart. For more conventional structures he commented that "closer
> >is better".
> >
> >There has been a great deal of misinterpretation of what the results meant
> >in Todd's earlier article, and the Interview was an attempt to help clarify
> >some of the questions.
> >
> >Doug
> >
> >At 07:42 AM 11/13/00 -0800, you wrote:
> > >I would like to call you attention to:
> > >
> > >"Power Bus Decoupling on Multilayer Printed Circuit Boards" by Hubing,
> > >Drewniak, Van Doren and Hockanson, published in the May 1995 IEEE
> > >Transactions on Electromagnetic Compatibility, Vol. 37, No.2.
> > >
> > >Among their conclusions is that "on printed circuit boards that do have
> > >internal power and ground planes, all decoupling capacitors are shared in
> > >the frequency range in which they are effective (typically below 200-300
> > >MHz), and the location of a decoupling capacitor on the board is relatively
> > >unimportant."
> > >
> > >It appears to be more important to have the shortest possible connections
> > >between the decoupling capacitors and the power and ground planes than
> > where
> > >they are on the board.
> > >
> > >Thomas L. Jackson, P.E.
> > >Staff Product Development Engineer
> > >Network Access Development
> > >Systems Solutions Group
> > >3545 North First Street
> > >San Jose, CA 95134-1804
> > >telephone: (408) 922-9574
> > >facsimile: (408) 922-9618
> > ><>

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