RE: [SI-LIST] : Connector pin pwr/gnd ratio

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From: Larry Miller (ldmiller@nortelnetworks.com)
Date: Tue Nov 14 2000 - 07:33:44 PST


If the currents are flowing between the voltages and grounds, proportion
according to current; i.e., equalize the current in the pins. Thus the
number of ground pins should equal the sum of the pins used for the
voltages. This is the "DC" solution.

However, the more usual case is that you have return currents from high
speed logic, etc., and this means that you have to distribute the pins in
the connector to minimize inductances and current loop areas.

Usually, if you are feeding power to a PCB you have a major decoupling
network (bulk cap plus hf bypassing) right after the power enters the board,
so you can kind of consider the power pins to be operating in "DC mode".

If you have signal lines in the same connector you want to intersperse the
grounds amongst the signals to give lowest-inductance/loop area paths. This
may mean you need extra grounds. I usually try to make sure that each signal
can "see" an adjacent ground pin at least.

Howard Johnson deals with this at length in the "Digital Black Magic" book.

Larry Miller

> -----Original Message-----
> From: Peterson, James F (FL51) [SMTP:james.f.peterson@honeywell.com]
> Sent: Monday, November 13, 2000 1:44 PM
> To: si-list@silab.eng.sun.com
> Subject: RE: [SI-LIST] : Connector pin pwr/gnd ratio
>
> The original question was meant to be:
>
> On my board (CMOS logic), I have 85 connector pins allotted for 3.3v, 2.5v
> and gnd.
> How would you distribute? and why?
>
> Would you do 25% for 3.3v, 25% for 2.5v, and 50% for gnd? (which is a
> component approach, but maybe not a board approach.)
>
> Would you minimize the pwr pins and maximize the gnd pins? if so, why?
> (don't we have return currents flowing in both.)
>
> all inputs and opinions are welcome and appreciated.
>
> Jim
>
>
> -----Original Message-----
> From: Charles Grasso [mailto:chasgra@msn.com]
> Sent: Monday, November 13, 2000 4:25 PM
> To: Peterson, James F (FL51); si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Connector pin pwr/gnd ratio
>
>
> The allocation of grounds with respect to any number of signals is mainly
> based
> on rise time (hence frequency content). That is to say the faster the rise
> time the
> more grounds you need - the asymptote being a solid "bar" connection found
> in many impedace controlled connectors.
>
> ----- Original Message -----
> From: "Peterson, James F (FL51)" <james.f.peterson@honeywell.com>
> To: <si-list@silab.eng.sun.com>
> Sent: Monday, November 13, 2000 6:57 AM
> Subject: [SI-LIST] : Connector pin pwr/gnd ratio
>
>
> > Hello,
> >
> > I'm looking for some information on what the pwr/gnd ratio should be for
> a
> > board's connector. (I know there is something in the archives, but I
> > couldn't find it.)
> >
> > Someone said a rule of thumb is a 3 to 1 ratio, but I'm not sure what
> that
> > is based on.
> >
> > So let's say for example I have 85 connector pins for 3.3v, 2.5v and
> gnd.
> > How would you distribute? and why?
> >
> > thanks
> > Jim
> > > Jim Peterson
> > > james.f.peterson@honeywell.com
> > > Honeywell Space Systems
> > > M/S 934-5
> > > 13350 U.S. Hwy 19 N.
> > > Clearwater FL, 33764-7290
> > > Office : 727-539-2719
> > > Fax : 727-539-2183
> >
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