[SI-LIST] : Via effects on the plane inductance

From: Brian Seol ([email protected])
Date: Mon Nov 13 2000 - 17:07:08 PST

• Next message: Ozgur Misman: "[SI-LIST] : current carrying capacity of chip bump and solder ball??"
• Previous message: Kim Helliwell: "[SI-LIST] : How are Switch Groups and Series Switch models used?"

Hello all,

I have a simple question about the effects of the number of vias on the
power and ground plane inductance of multilayer packages such as PGA, BGA
and MCM. Can you please provide guidelines on the number of vias or
separation between two neighboring vias for the effective design of power
and ground planes.

I guess, plane inductance decreases upon an increase in the number of via
and inductance values decrease to a low asymptote when there is a large
enough number of vias. After this point, plane inductance increases caused
by decreasing the plane area due to vias. Is this right? need any
trade-off? Any comments will be appreciated.

B. Brian Seol
Tessera Inc.
Signal Integrity Engineer
San Jose, CA, USA
[email protected]

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

• Next message: Ozgur Misman: "[SI-LIST] : current carrying capacity of chip bump and solder ball??"
• Previous message: Kim Helliwell: "[SI-LIST] : How are Switch Groups and Series Switch models used?"

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:30:07 PDT