Re: [SI-LIST] : deCoupling caps and there placement

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From: Doug Brooks ([email protected])
Date: Sun Nov 12 2000 - 16:50:01 PST

I look at it this way. Think of the cap as a (temporarily) pure voltage
source (a bucket of electrons). The culprit is the inductance in the

Now, where do you want the lowest voltage drop? Between the ground plane
and the negative pin of the device? Or between the positive plate of the
capacitor and the power pin of the device? (There will be a little voltage
drop BOTH places. The question is, which one do you want to minimize?)

I believe the answer is that you want the lowest stray voltage drop between
the reference voltage for the device and the REFERENCE voltage on the
plane. The reference voltage is usually ground. Therefore, you want to
minimize the stray voltage between the ground plane and the ground pin of
the device. Therefore, place the cap with the ground pin closest to the
device's ground pin. In ECL circuits, the "reference" voltage is the high
voltage (zero) with the power supply voltage being negative. Again, place
the cap closest to the reference (ground). In CMOS circuits, the
"reference" tends to be half way between the power and ground voltages. In
that case, place the cap equally between the two pins!

But, there are as many differences of opinion about this as there are

Doug Brooks

At 03:10 PM 11/10/00 -0800, you wrote:
>I just heard a school of thought that says place decoupling caps
>physically as close as possible to GND pins....I have always keep the
>lead length as short as possible to the VCC pin which decouples the
>power pins. I understand that one should keep the ground lead as short
>as possible also ... so if one has a trade off to make , which lead
>should be longer and why...??? any thoughts

Doug Brooks' book "Electrical Engineering for the Non-Degreed
Engineer" is now available. See our web site for details.
Doug Brooks, President [email protected]
UltraCAD Design, Inc.

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