RE: [SI-LIST] : Possible TDR microstrip measurement error?

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From: Willis, Ken (
Date: Fri Nov 10 2000 - 15:34:19 PST

Hi Eric,
I was just starting to write some of the same comments when I read this
message from John. I started out in PC fab way back when, and built and
TDR'd more impedance controlled boards than I want to remember (still
recovering from the fumes coming off the cupric chloride etch line).
Meeting microstrip impedance specs was usually a bit more
challenging, for a couple of reasons.
    - We were doing mostly foil construction externally, so that first
dielectric was usually prepreg instead of pre-cured core material, so
you'd get some variation there in thickness.
    - Boards electroplate from the "outside in", so you get variation in
trace thickness across the panel. The impedance coupons are always on
the edge of the board, so they plate up pretty high. If you start with
1/2 oz copper (.7 mils), it would generally plate up to 2.1 or so.
    - If you get variation in trace height, you will also get variation
in finished trace width due to the etching process. Taller traces will
see less line width reduction but more trapezoidal shape than the lower
    - Most of our boards then were SMOBC (solder mask over bare copper),
so in theory you should be designing them as buried microstrips, with a
couple mils of soldermask over the traces, then air. But try getting Er
values from a soldermask vendor. I didn't have any luck, so empirically
you TDR the boards after external etching, and make sure
you are 3 ohms or so over nominal. Then applying the mask generally
dropped the measurement back into mid-range.
So you add all these variables up, plus the mistake some may make of
using Er of FR4 above and below the trace in the model, and you have a
recipe for confusion. Hence the empirically-derived fudge factors by
every fab shop.
My recommendation to those on the SI list is that if you really have
traces where the Zo is that critical, do NOT put them on external
layers. There is too much process variation there.
You will get a lot more consistency on non-plated 1/2 oz. inner layers.
And don't kid yourself into thinking that because you spec'd external
layers +/- 10% that you got it. You have probably just bought a batch of
impedance-controlled coupons. There will be significantly
more variation in thickness, line width, and Zo across that 18x24 panel.
Some board shops will do better than others, but in general impedance
controlled microstrips are tougher to do well.
Ken Willis
Sycamore Networks

-----Original Message-----
From: JNH []
Sent: Thursday, October 26, 2000 10:30 PM
To: Eric Bogatin
Subject: RE: [SI-LIST] : Possible TDR microstrip measurement error?


For microstrip line measurement, I think we need to consider the solder
mask, covering the microstrip line with 0.7~1.0 mils thickness. So, the
microstrip line is an embeded microstrip line not pure microstrip. I
the polar tool -- CITS25 to do calculate the microstrip and substrate
ohms to compensate the effect of solder mask. The TDR measurment shows
bigger deviation for microstrip line than that of stripline. I believe
it is
caused by more processing needed for the outer layers of a PCB, such as
solder platting and solder mask. A 0.5 oz (0.7mils) thickness copper
finally be added up to 2.0 mils for the outer layers.


Best Regards,

John Lin
SI Engineer, ARD4
Quanta Computer Inc.,Taiwan, R.O.C.
Tel: 886+3+3979000 ext. 5183

-----Original Message-----
From: Eric Bogatin [ <> ]
Sent: Friday, October 27, 2000 5:17 AM
To: Sun. COM
Cc: eric
Subject: [SI-LIST] : Possible TDR microstrip measurement error?

After a recent talk I gave on TDR measurements, I was approached by a

from the IPC (I apologize that I did not catch your name, whoever you

with a problem that might be common in the board fab industry. I wanted
get comments from folks on the SI list as to whether you have
this problem or is it so obvious that everyone knows to watch out for

In some shops, a TDR is used to measure the dielectric constant of the

material using test lines on coupons. Given the physical length, L, and
time delay, TD, for the one way trip (i.e., 1/2 the time measured by the

for an open terminated line), the speed of light in the material can be
calculated as vel = L/TD. The dielectric constant is calculated as

x 10^8 m/sec / vel). This is the straight forward part.

When the trace is a stripline, the dielectric constant extracted is the

dielectric constant of the material surrounding the traces. This value

be put in a field solver to use to help predict the design rules for
made with this material. I have had success in predicting board trace
impedance to better than 2% with some field solvers, limited to how well
knew the cross section and dielectric constant.

However, when the test line is a microstrip, some of the field lines are
air, and the dielectric constant calculated in this way is the
dielectric constant, not the board's bulk dielectric constant. Yet, I am
told some board shops use this measurement from microstrips to get a
for what they think is the bulk dielectric constant of their material
then use this value in a field solver or approximation. Of course, their
predictions from the field solver- anyone's- would be off by as much as
10%-20%, for the measured impedance of the test lines. I suspect this is

basis for the comments I have heard that some fab shops are not happy
their field solvers- that they have had to add their own correction
to the many approximations that are out there and each shop has their
oracle they consult to design a controlled impedance board.

There is still value in the effective dielectric constant. From the
microstrip test line cross section, a 2D field solver can be used to

what bulk dielectric constant the material under the trace must have had
result in the measured effective dielectric constant. If the board shop

this extracted value for the bulk dielectric constant, their following

solver results would probably be much more accurate.

has anyone else encountered this problem in board shops?

all comments are welcome.


Eric Bogatin
Training for Signal Integrity and Interconnect Design
v: 913-393-1305
f: 913-393-1306
web: <
<> >

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