From: Michael Nudelman (firstname.lastname@example.org)
Date: Mon Nov 06 2000 - 06:15:24 PST
You are right - state machines of the PCI devices use only rising edge. But:
if you see timing of, say, V-Cube's (or QLogic's) PCI peripherals, you will
notice, that the actual data (parity bit etc) are output with such a delay,
that they are very close to falling edge of the clock.
That is why I usually assume timing from falling edge to the next rising edge
(the data are output on one rising edge and sensed by opposite party on the
next rising edge). This gives me safer timing estimate.
"Ingraham, Andrew" wrote:
> >Now, the data are output by
> >transmitter on falling edge of the clock, with some delay.
> PCI uses only the rising edge of the clock. The falling edge is not used.
> Timing is cycle-to-cycle between rising edges, with no half-cycle events.
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
> email@example.com. In the BODY of message put: UNSUBSCRIBE
> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
**** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:29:59 PDT