From: Michael Nudelman (email@example.com)
Date: Mon Nov 06 2000 - 06:15:24 PST
You are right - state machines of the PCI devices use only rising edge. But:
if you see timing of, say, V-Cube's (or QLogic's) PCI peripherals, you will
notice, that the actual data (parity bit etc) are output with such a delay,
that they are very close to falling edge of the clock.
That is why I usually assume timing from falling edge to the next rising edge
(the data are output on one rising edge and sensed by opposite party on the
next rising edge). This gives me safer timing estimate.
"Ingraham, Andrew" wrote:
> >Now, the data are output by
> >transmitter on falling edge of the clock, with some delay.
> PCI uses only the rising edge of the clock. The falling edge is not used.
> Timing is cycle-to-cycle between rising edges, with no half-cycle events.
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