Re: [SI-LIST] : Noise on Ref Planes/Decoupling

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From: David Instone (david_instone@uk.xyratex.com)
Date: Fri Nov 03 2000 - 08:55:18 PST


Arthur,
  Had a case like this just recently, Turned out to be that every time
the ram was refreshed (60kHz) it modulated the output from the
oscillator module that was the master osc for the 1Gbd fibre channel
output.
 On a spectrum analyser it showed up as spikes at 60khz intervals either
side of the 1/2 baud rate frequency. On the power rails the spectrum
analyser showed a VERY small spike at 60khz. A one inch square single
turn loop connected to the analyser input and held near the dc power
leads to the PCB showed a very large spike at 60kHz.

  Anyway the oscillator was fed via a SMD ferrite bead and cap etc, but
at 60kHz that's no use. A few millimeters away there was a SMD 3
terminal 3.3 volt regulator, I lifted the 'input' end of the ferrite,
took a short length of hookup wire from there to the output of that
regulator and the problem ceased to exist.

Morals
  a. remember that oscillators need low frequency decoupling as well as
the higher frequencies.
  b, buy a spectrum analyser <g>

Regards

Dave Instone. Compliance Engineer
 Test Systems, MP24/22
 Xyratex, Langstone Rd., Havant, Hampshire, P09 1SA, UK.
Tel: +44 (0)23-92-496862 (direct line)
Fax: +44 (0)23-92-496014
http://www.xyratex.com Tel: +44 (0)23-92-496000

 
ARTHUR BROWN wrote:
>
> Hello SI experts,
>
> I have a 12 layer board. The board has 2 power
> planes, 4 ground plane and 6 signal planes.
>
> This is a digital board with processor, memory,
> glue logic, framers, packet processors etc.
>
> The framer requires very low jitter clock.
> This clock is coming into the card at
> 77.76 Mhz PECL differential. The clock is
> first buffered using a PECL buffer. Then
> clock is translated using PECL to TTL
> translator and given to the framer.
>

> Now my problem.
>
> When there is no activity on the card there
> is a certain value of jitter on the clock
> at the framer. Now I generate activity on
> the board - processor does continuous
> memory accesses and enable packet transfer
> processing/framing etc. at full rate.
> Then the jitter on the clock at the framer
> is considerably higher.
>
> Now my question
>
> Will I attribute the above observation to
> noise on the Ref planes due to return
> current paths.
> I think not because the TTL clock is
> routed through an inner stripline layer
> and separated from all other traces by
> 150 mil on either side for all traces
> between the ref planes of this stripline
> layer. Does anyone think otherwise.
>
> Or
>
> Will I attribute it to improper power
> plane decoupling.
>
> If so then how do I analyse for
> power plane resonance due to capacitor
> lead, via, pad inductance for the few
> hundred decoupling capacitors I have
> on the board. Are there any tools which
> does this.
>
> Any help, insight, suggestions will
> be highly appreciated.
>
> Regards,
>
>
>
> =====
> Arthur Brown
> HSSI Consulting,
> 16 Ang Mo Kio Street 80 - Level 4
> Ang Mo Kio Industrial Park 4,
> Singapore-569088
> Tel:(65)489 9999
> email: arthown@yahoo.com
>
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