RE: [SI-LIST] : PCI Bus propagation delay measurement

From: Ingraham, Andrew ([email protected])
Date: Fri Nov 03 2000 - 07:36:02 PST

> This test load thing is still a bit unclear to me. Isn't the purpose of
> the
> specified
> 25ohm test load just to specify the minimum and maximum drive capability
> so that it would work in any system.

No. The DC specs and V/I curves do that.

In order to add up the numbers (Tval + Tprop + Tsetup + Tskew < Tcycle),
Tval and Tprop need to be measured/specified under the same conditions, so
that their sum equals the delay from clock at the sending IC, to the input
at the receiving IC.

Ideally, Tval would be specified using the actual electrical load you have
on the IC in YOUR circuit. Then you would know that the signal at the IC's
output pin behaves exactly the same when you put it on your board, and you
can simply measure Tprop by probing the two ends of the trace, measuring
their difference, and be done with it.

But Tval is never measured using YOUR board.

How, then, do you handle Tval and Tprop so that their sum equals what you
want? That's the problem.

To do this right, take the vendor's Tval (using whatever test load he uses),
and then simulate the device in your circuit. Measure the difference
between the signal at your destination IC, vs. the signal at a test load
which is the same as the vendor's. Their difference is Tprop. Then when
you add Tprop to Tval, you get the true delay from the input pin to the
destination, without you having to simulate the whole delay path in the
vendor's IC. In theory this should work for any test load the vendor
chooses, but it works better when the test load comes close to presenting
the same electrical characteristics to the driving IC as your actual circuit
would.

In the old days (i.e., TTL), vendors used a test load of typically 50pF in
parallel with some moderate resistance to some voltage. As long as your
individual gate delays, and maybe adding something for the flight times of
the wires. For most TTL and early CMOS, the loaded rise times tended to be
slower than the trace delays, so you could treat your real load as if it was
a lumped capacitance. This method worked because your real load was usually
less than 50pF, so it was conservative and you were safe.

Well, this is no longer true. As risetimes get faster, you can't treat your
load as lumped anymore, you have to think of it as a collection of
transmission lines. And it is no longer desirable to be conservative on
be. (Not to mention the fact that it may not be conservative anymore, due
to the fact that the real load isn't as lumped as we previously assumed.)

Consider a PCI device in (say) the first slot, somewhere in the middle of
the bus traces. Its driver "sees" both halves of the bus as if they were in
parallel.

When a fast driver switches, for a brief moment (until the round-trip t-line
delay) it sees a t-line as if it were a resistance (equal to Zo) connected
to the bus's previous voltage.

maybe 50 ohms or less including loading from other devices on the bus. So,
for the first one to three nanoseconds. That is the justification for using
the 25 ohm test loads; they mimic the bus during the first couple of

> How about in this 'known' bus system? Would I still need to calculate the
> starting point for Tprop? I could insted just measure what is happening
> in the bus (Driving Bus curve) like in picture 7-10 of the PCI2.2 spec.

No, you really need to measure in such a way that you account for the
interaction between driver and load, because the number you have for Tval is
referenced to the Test Load. Using the method prescribed in the PCI Spec
does this (by referencing the start of Tprop to the Test Load waveform).

Consider a PCI device driving a 1" trace to a 100pF capacitor. If you put
your scope probes on the two ends of the 1" trace, you might conclude that
Tprop is only 0.18ns. That's the flight time, but it doesn't represent the
delay of the 100pF load, compared to the Test Load, which is what Tprop is
supposed to measure.

> If I was to simulate Tval I think I would also need to know what are the
> delays for logic inside the device plus the driver delays.
> I guess I would have some difficulties getting models for a chip's
> internal logic.

You don't need to simulate all of Tval. All you need to do is simulate the
driver (the vendor's output stages) driving the test load and driving your
real load. You need both the "Driving Test Load" and "Driving Bus"
waveforms for comparison, as in Figure 7-10.

Andy

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