Re: [SI-LIST] : Unit failing ESD testing

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From: jrbarnes@lexmark.com
Date: Fri Nov 03 2000 - 06:11:25 PST


Jeff,
This is a set of guidelines that I put together seven years ago for my
department, on ways to harden electronic devices against Electrostatic Discharge
(ESD). The three main strategies are:
1. Prevent an ESD arc from occurring.
2. Prevent coupling to ESD-sensitive circuits.
3. Add redundancy (memory, circuits, time) and checking to the design to permit
detection/correction of random errors.

                                                   John Barnes Advisory
Engineer
                                                   Lexmark International

                DESIGNING ELECTRONIC EQUIPMENT FOR ESD-HARDNESS

       Sources of ESD Threats:
        Charged person touches the equipment.
        Charged person touches the table beneath the equipment.
        Moving paper/parts inside the equipment build up a charge.
        Charged furniture touches the equipment.
        Charged furniture touches uncharged/oppositely-charged
          furniture near the equipment.

       Levels of ESD Threats:
        Voltages up to 20kV (Straus, Capps, Boxleitner, Pepe,
          Mardiguian) OR 15kV (Leibowitz) OR 25kV (Paul) OR 35kV (Ott,
          Welsher).
        Currents up to 200A (Boxleitner) OR 100A (King).
        Electric fields up to several hundred kV/m (Mardiguian) OR
          3 MV/m (King).
        Rise times of 0.2ns to 70ns (frequencies up to 5GHz).
        Initial 0.5-10ns spikes, followed by 100ns to 2000ns pulses.
        May have multiple discharges separated by 10us to 200ms.
        Highest voltages not necessarily the worst-- lower ESD voltages
          often have faster edge rates.

       Effects of ESD:
        Conducted coupling tends to cause damage.
        Radiated coupling tends to cause upsets/errors.

       ESD Testing:
        Test equipment in operating & installation configurations.
        Keep ground strap of ESD simulator perpendicular to the
          suspected discharge path or electrically far from the
          unit-under-test.
        Test to IEC 801.2 level 3:
          - 8kV air-discharge without failure.
          - 15kV air-discharge without damage.
          - 8kV contact-discharge without damage.
          - Check any exposed metal, including connector pins.
          - Check ventilation holes, controls, and seams in case.
        Discharge to a horizontal/vertical coupling plane with all
          cables attached & again with everything but the power cable
          detached. Shows you whether the cables or the basic design/
          shielding is weak.
        If a few spots are vulnerable, turn out lights & zap the
          product to see path of discharge-- may be able to fix easily.
        With an emulator, change registers/stack-pointers/program
          counter to random values to simulate ESD-induced changes and
          see what happens to the equipment.
        At critical junctions in the code toggle an unused output pin,
          once at point #1, twice at point #2, etc. Can monitor this
          pin with an oscilloscope to see what the code is doing.

       Overall Strategies:
        Prevent ESD discharges.
        Prevent coupling of ESD into circuits/devices.
        Increase noise immunity of devices/circuits.

                         HOW TO PREVENT ESD DISCHARGES

       

-1Enclosure Design to Prevent ESD Discharges:-0
       1. Insulating barriers prevent conductive coupling, but don't
           affect radiated ESD.
       2. Set breakdown level of enclosure > 20kV by thin high-
           dielectrics or air gaps > 10-13mm.
       3. Keep operator > 20mm from electronics/ungrounded metal.
       4. Keep ungrounded enclosure metal > 20mm from exposed
           electronics (Boxleitner) OR > 8.4mm (Ott) OR > 10mm (Paul) OR
> 9.5-12.7mm (Straus).
       5. Keep grounded un-insulated enclosure metal > 2.2mm from
           exposed electronics (Boxleitner) OR > 0.5mm (Ott) OR > 1mm
           (Paul).
       6. Position seams/openings to provide clearance from conductive
           parts.
       7. Use tongue-in-groove or shiplap joints.
       8. Use mylar tape where clearance is limited.
       9. Cover keyholes with tape extending > 13mm past edge of holes.
       10. Avoid sharp edges/points on metal components.
       11. Recess sensitive signals at connectors, making them difficult
           or impractical to touch manually.

       -1Cabling Design to Prevent ESD Discharges:-0
       12. Space wires/connector pins by > 2.2mm to prevent arcing.
       13. Cover unused/rarely-used connectors with plastic dust
           covers.

       -1Circuit Board Layout to Prevent ESD Discharges:-0
       14. Isolate electronic components from the ESD source, > 20mm
           away from areas/ungrounded metallic items that the operator
           can touch.
       15. Make conductor corners rounded to prevent arcing (heatsinks
           or any other metal items close to areas that a person can
           touch).
       16. Recess LED's & cover them with light pipes/tape.
       17. For membrane keyboards extend border to increase path length.
       18. For membrane keyboards use plastic bezel to increase path
           length.

                  HOW TO PREVENT COUPLING OF ESD INTO CIRCUITS

       -1Enclosure Design to Prevent Coupling of ESD into Circuits:-0
       19. Conductive barriers prevent conductive coupling & reduce
           radiated ESD-- 2mm separation between grounded shield &
           circuitry will prevent secondary arcs (up to 20mm separation
           needed for ungrounded shield).
       20. Use multipoint grounds in areas that you want ESD current to
           flow.
       21. Use single-point grounds in areas that you don't want ESD
           current to flow.
       22. Connect metal portions of enclosure to chassis ground.
       23. Keep bonding jumpers short and wide, well away from sensitive
           electronics.
       24. Grounded parts should have > 1500V isolation to circuitry.
       25. Ungrounded parts should have > 25000V isolation to circuitry.
       26. Try to put all cable entries close to center of enclosure.
       27. Provide chassis ground within 40mm of each cable entry.
       28. Keep seams & openings > 10-13mm away from grounds & sensitive
           signals/devices.
       29. Keep conductive parts (screws) penetrating shields well away
           from circuitry.
       30. Radiated noise entering hole depends on longest dimension, so
           keep slots/holes < 20mm long.
       31. Use several small openings instead of one big opening.
       32. Space openings apart by their largest dimension.
       33. Perforate shields by deep holes with no conductors inside,
           acting as waveguides below cutoff to attenuate noise.
       34. Provide for shielding, to be added if needed.
       35. Tie shields to circuit common.
       36. Tie shields to conductive exit points for ESD charges--
           connectors, switches on battery-operated devices, green wire
           ground on line-operated devices.
       37. Put a ground plane underneath cards, parallel and close to
           them. Connect grounds of peripheral cables to this ground
           plane at their entry point.
       38. Put a secondary shield between the enclosure and circuitry,
           tied to circuit ground for I/O shielding & bypassing.
       39. Put grounded conductive shields behind control panels to act
           as spark arrestors.
       40. Choose shield materials to minimize corrosion (< 0.75V EMF).
       41. Avoid nicks, cracks, thinning of conductive shields.
       42. Overlap shield seams by > 5x the gap.
       43. Electrically connect seams in shields every 20mm with
           fasteners/gaskets to shorten slots.
       44. Connect foil tapes to rest of shield.

       -1Cabling Design to Prevent Coupling of ESD into Circuits:-0
       45. Use multipoint grounds where you want ESD currents to flow.
       46. Use single-point grounds where you don't want ESD currents to
           flow.
       47. Keep I/O cables well away from ground straps & pieces of the
           enclosure that may carry ESD current.
       48. Flat cables should have at least 1 ground next to each signal
           line (S-G-S-S-G-S-...S-G-S), with sensitive signals at the
           center of the cable. Grounds should be connected at each
           connector. If you must have a single-point ground system to
           prevent ground loops, directly connect a ground wire to ground
           at one connector and use capacitors for low-frequency
           isolation at the other connectors.
       49. Use shielded cables with shields tied to chassis ground at
           each connector.
       50. Connect cable shields to chassis grounds with high-frequency
           connections (360 degrees preferred) within 40mm of each cable
           entry point.
       51. Keep unshielded portions of cable < 40mm long.
       52. If you don't have a chassis ground, tie cable shield to logic
           ground with a 1-10nF capacitor (3.9nF 1kV is good).
       53. Prefer foil- or foil-and-braid-shielded cables
       54. Keep cable shields > 0.025mm thick.
       55. Either clip off extra lines so they are within the shield, or
           parallel them with other lines.
       56. Space wires/connector pins by > 2.2mm to prevent arcing.
       57. Prevent constant current flow through grounding contacts.
       58. Metals in contact should have an electromotive force < 0.75V.
       59. Prefer cathodic materials.
       60. Make anodic (positive) items bigger than the cathodic
           (negative) items.
       61. Use common-mode chokes on signals & signal grounds but not on
           shields (Boxleitner); on entire cable (Straus, Paul).
       62. Put ferrite beads on ground/power/signal lines, but not on
           shield conductors.
       63. Do not pass ESD current through a ferrite bead.
       64. If used, put ferrite beads near receiver end.
       65. Put over-voltage clamping devices close to cable entry points.

       -1Circuit Board Layout to Prevent Coupling of ESD into Circuits:-0
       66. Put all connectors in one area.
       67. Keep I/O devices close to I/O connectors.
       68. Use multipoint grounds where you want ESD currents to flow.
       69. Use single-point grounds where you don't want ESD currents to
           flow.
       70. Minimize power-to-ground loop areas by gridding power &
           ground, or by using multilayer boards.
       71. Put small bypass caps close to each connector and each module
           (at least every 80mm).
       72. Use wide chassis ground lines (length-to-width < 5:1).
       73. Fill in unused areas with ground, connected at least every
           60mm.
       74. Put a chassis-ground guard ring around the periphery of a
           board, and around mounting holes, in all layers with frequent
           vias to tie the layers together.
       75. Leave solder mask off the guard ring on the top & bottom
           layers.
       76. Connect connector housings and metal switch housings to
           chassis ground.
       77. For membrane keyboards use a grounded peripheral guard ring.
       78. Keep un-insulated chassis ground > 2.2mm from other traces.
       79. Minimize signal-to-ground loop areas. Signal lines must be
           < 13mm of ground. Signal lines over 300mm long must be
           paralleled by a ground.
       80. Keep signal lines short, feeding from the center of the net
           if possible.
       81. Connect L-C or ferrite bead-C filters on connector signals to
           chassis ground.
       82. Keep protective-component leads short.
       83. Build a Faraday cage around sensitive devices & their inputs.

       -1Circuit Design to Prevent Coupling of ESD into Circuits:-0
       84. Use low-impedance circuits wherever possible.
       85. Use differential signals wherever possible.
       86. Isolate signals with optoisolators or transformers.
       87. Tie unused inputs high or low (do not let float).
       88. Do not connect sensitive inputs to ESD-susceptible lines (i.e.
           microprocessor reset to a long cable).
       89. Put a ferrite bead between chassis ground and logic ground.
       90. Put a ferrite bead in each power line at entry point to card.
       91. Put a surge suppressor/MOV/capacitor between each power pin &
           chassis ground.
       92. Filter each sensitive input within 25mm of device pin:
           - Protect reset/interrupt lines.
           - Capacitors to chassis ground if possible; otherwise to
              logic ground.
           - Wire to 100-1000pF capacitor to high-Z input.
           - Wire to capacitor to ferrite bead to low-Z input.
           - Wire to resistor/ferrite bead to capacitor to high-Z input.
       93. Put common-mode chokes on signals (note: may have adverse
           effect if ESD on shield induces noise on signals).
       94. Protect inputs with high-speed clamping suppressors.
       95. Series resistors and shunt diodes to I/O pins (up to 1k

-100k
           for MOS inputs, around 50 for bipolar inputs).

       

-1Component Selection to Prevent Coupling of ESD into Circuits:-0
       96. Use low-inductance capacitors for ESD filters (chip
           capacitors, ceramic discs, mica, glass).
       97. Use non-inductive resistors for ESD filters (carbon comp,
           film).
       98. Use high-frequency ferrite beads for ESD filters, resistive
           from 10MHz to 1GHz with a single-turn to minimize capacitive
           coupling.
       99. Choose transient suppressors that turn on within 1ns.

              HOW TO INCREASE NOISE IMMUNITY OF DEVICES/CIRCUITS.

       -1Circuit Design to Increase Noise Immunity:-0
       100. Do not use any circuit/system with an unlimited-duration
            wait/disable state.
       101. Put peripheral chip resets under software control.
       102. Avoid edge-triggered logic.
       103. Use strobes to latch data, not edges.
       104. Pull-up or pull-down unused inputs.
       105. Check parity & framing wherever possible.
       106. Double-check critical inputs several microseconds apart
            before using them.
       107. Read outputs back & verify that they match the intended
            value.
       108. Provide redundant hardware.
       109. Provide a hardware watchdog timer to monitor program flow.
            The software in turn monitors the watchdog timer, and resets
            it periodically using an edge-trigger. If the watchdog timer
            times out, it either resets the processor or forces a
            non-maskable interrupt.

       -1Component Selection to Increase Noise Immunity:-0
       110. Do not push components to their limits.
       111. Use slow, insensitive components wherever possible.
       112. Use differential I/O instead of single-ended I/O.
       113. Use chips with read-back capability (read-only or read/write
            registers).
       114. Use chips with high immunity to ESD (table taken from Capps):
            Charles, "ESD: A Threat to Buried Circuits", EMC Technology,
            Vol. 6, No 7, November-December 1987, pp39-42):

            -1DEVICE TYPE-0 -1RANGE OF ESD VULNERABILITY
(VOLTS)-0
            VMOS 30-1800
            MOSFET 100-200
            GaAsFET 100-300
            EPROM 100
            JFET 140-7000
            Op Amp 190-2500
            CMOS 250-3000
            Schottky Diodes 300-2500
            Film Resistors 300-3000
            Bipolar Transistors 380-7000
            ECL 500-1500
            SCR 680-1000
            Schottky TTL 1000-2500

       -1Software Design to Increase Noise Immunity:-0
       115. Provide protection from program flow errors (skip steps or
            jump to unused address).
       116. Place trap/return codes in code tables & unused areas.
       117. Fill unused ROM with NOP's, ending with a jump to an error
            routine.
       118. Put jump to error routine in all unused interrupt vectors.
       119. Include a check for excessive count in delay loops.
       120. Check index registers & other important registers before use.
       121. Write a token before entering a routine & check before
            returning.

       122. Verify stack empty when in main program & when tasks finish.
       123. Check stack pointer before a return & periodically in main
            program.
       124. If using a real-time executive, verify that task is valid for
            that time whenever a task exits/suspends.
       125. When jump to a subroutine, copy the new stack data to a
            second stack. On return verify that the main stack & the
            copy match.
       126. Include checkpoint variables to verify orderly program flow.
       127. Run watchdog routines periodically to make sure that program
            has performed periodic functions & therefore program flow
            okay. Main program in turn verifies that watchdog routines
            are running.
       128. At regular intervals:
            - Re-enable interrupts.
            - Reread control/selection inputs.
            - Refresh output ports.
            - Check/refresh/recover memory.
       129. Validate data when received.
       130. Check data from humans for syntax and validity.
       131. Acknowledge all valid inputs & retransmit data if don't get
            acknowledgement.
       132. Check inputs for reasonable/valid values (range/consistency/
            parity/framing/checksum/CRC/error-correcting-code checks).
       133. Sample inputs twice for software filtering.
       134. Re-validate data just before using it.
       135. Store critical data in multiple locations. Periodically
            crosscheck these locations & fix mismatched data.
       136. Use parity/checksums/CRC's/ECC's to check blocks of data.
       137. Break large tables into fixed-length records with checksums.
       138. Work on a copy of a record, then overwrite the original.
       139. Use a maximum depth counter when searching linked lists.
       140. Maintain a copy of all output states in memory.
       141. Check outputs by having receiver echo data.
       142. On finding an error, recheck hardware/ROM/RAM, all programs,
            and all data.
       143. Consider shutting down if the error rate gets too high.
       144. If you detect an incorrect state, try to re-establish the
            previous correct state. If this can not be determined,
            switch to the most-likely state that causes the least-serious
            problems. Warn any attached units that you have just
            performed an error recovery.
       145. To restore the state:
            - Reset stack pointers.
            - Reset FIFO's.
            - Reset counters.
            - Prevent transmission of suspect codes.
            - Disable interrupts during restoration, then re-enable &
               start timers.
            - Reset pending interrupts.
            - Refresh outputs.
            - Send host a code that restoring state.
            - Fix whatever failed the sanity check.
       146. Keep errorlog in RAM of the last few fix-ups, that can be
            dumped for analysis.

                                   REFERENCES

       Boxleitner, Warren, -1Electrostatic Discharge and Electronic-0
       -0Equipment-0, IEEE Press, New York, 1989.

       Boxleitner, Warren, "How to defeat electrostatic discharge",
       -1IEEE Spectrum-0, Vol. 26, No. 8, August 1989, pp. 36-40.

       Capps, Charles, "ESD: A Threat to Buried Circuits", -1EMC-0
       -1Technology-0, Vol. 6, No. 7, November-December 1987, pp. 39-42.

       Gerke, Daryl, "Designing Noise Tolerance into Microprocessor
       Systems", -1EMC Technology-0, Vol. 5, No. 2, March-April 1986,
       pp. 45-52.

       Jarrett, Dick, "Software fault tolerance staves off the errors
       that besiege

P systems",

-1Electronic Design-0, August 9, 1984,
       pp. 187-202.

       Mardiguian, Michel, -1Electrostatic Discharge-0, Interference
       Control Technologies, Gainesville, VA, 1986.

       Ott, Henry, -1Noise Reduction Techniques in Electronic Systems,-0
       -12nd edition-0, John Wiley & Sons, New York, 1988.

       Paul, Clayton, -1Introduction to Electromagnetic Compatibility-0,
       John Wiley & Sons, New York, 1992.

       Straus, Isidor, "Designing for Compliance: Immunity to ESD",
       -1Compliance Engineering-0, Vol. 7, No. 2, Winter 1990, pp. 15-26.

       esd-hard.txt John Barnes 8/27/93

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