From: ARTHUR BROWN (firstname.lastname@example.org)
Date: Fri Nov 03 2000 - 04:13:53 PST
Hello SI experts,
I have a 12 layer board. The board has 2 power
planes, 4 ground plane and 6 signal planes.
This is a digital board with processor, memory,
glue logic, framers, packet processors etc.
The framer requires very low jitter clock.
This clock is coming into the card at
77.76 Mhz PECL differential. The clock is
first buffered using a PECL buffer. Then
clock is translated using PECL to TTL
translator and given to the framer.
Now my problem.
When there is no activity on the card there
is a certain value of jitter on the clock
at the framer. Now I generate activity on
the board - processor does continuous
memory accesses and enable packet transfer
processing/framing etc. at full rate.
Then the jitter on the clock at the framer
is considerably higher.
Now my question
Will I attribute the above observation to
noise on the Ref planes due to return
I think not because the TTL clock is
routed through an inner stripline layer
and separated from all other traces by
150 mil on either side for all traces
between the ref planes of this stripline
layer. Does anyone think otherwise.
Will I attribute it to improper power
If so then how do I analyse for
power plane resonance due to capacitor
lead, via, pad inductance for the few
hundred decoupling capacitors I have
on the board. Are there any tools which
Any help, insight, suggestions will
be highly appreciated.
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