From: [email protected]
Date: Fri Nov 03 2000 - 02:24:59 PST
Hi Mike,
I believe that if the device would start to drive the line on a falling
edge, the Tval would be about 15ns which would be out of the spec
(max.11ns).
This test load thing is still a bit unclear to me. Isn't the purpose of the
specified
25ohm test load just to specify the minimum and maximum drive capability
so that it would work in any system.
How about in this 'known' bus system? Would I still need to calculate the
starting point for Tprop? I could insted just measure what is happening
in the bus (Driving Bus curve) like in picture 7-10 of the PCI2.2 spec.
If I was to simulate Tval I think I would also need to know what are the
delays for logic inside the device plus the driver delays.
I guess I would have some difficulties getting models for a chip's
internal logic.
It has been helpful to measure a real bus and see the relation to things
in the spec.
Timing and SI stuff is fun!
Br,
Marko
> -----Original Message-----
> From: EXT Michael Nudelman [mailto:[email protected]]
> Sent: 02. November 2000 19:28
> To: [email protected]
> Cc: [email protected]
> Subject: Re: [SI-LIST] : PCI Bus propagation delay measurement
>
>
> Marko,
>
> I forgot the terminology of the PCI a bit - but the Tprop, is
> is a round
> trip for the signal from the Transmitter to the closest end of the bus
> and then back to the receiver?
> If yes:
> Still, your period at 33Mhz is 30ns. Now, the data are output by
> transmitter on falling edge of the clock, with some delay. So you have
> roughly 13ns before the next rising edge, unless you use
> protocol, where
> you skip one clock. From these 13ns you have to deduct set-up time,
> which is what...5ns worst case or so? Minus your clock skew
> (minus 2ns,
> obviously, for the worst case)So you have about 6ns full trip time,
> which will translate into 36 inches roundtrip.
>
> If you have 24ns roundtrip time - this is too much.
>
> Mike.
>
> [email protected] wrote:
>
> > Hi SI people,
> >
> > When measuring a real PCI bus signal (not 25ohm test load);
> > Would the starting point of Tprop be for a rising
> > edge in this case at 0.285Vcc?
> >
> > Why Tprop isn't measured like in a TDR for example?
> >
> > Could this be possible in a 'known' system;
> > I would know exactly which PCI devices are going to be
> > connected to the bus.
> > I would have for example;
> > clock skew of 2ns
> > setup time 2ns
> > Tval 2ns
> >
> > Would Tprop of 24ns in this case be possible
> > for a 33MHz system?
> >
> > Br,
> > Marko
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