Date: Thu Nov 02 2000 - 10:11:57 PST
For a rough estimate, one could measure the time at the receiver and driver
when the voltage value is 0.285Vcc, subtract the two and get a Tprop.
Furthermore, you could probably use any level of voltage prior to when the
signal at the driving end plateaus. However, that doesn't account for any
reflections, signal degradation, or other problems one might see on its way
to a steady state. If you want a complete and accurate measurement of
Tprop, I would suggest subtracting the standard load as defined in the
If you have control over the entire PCI system you can choose your values
of Tskew, Tsu, Tval, and Tprop. Meaning, if you choose IOs that have the
characteristics listed below, Tsetup = 2ns, Tskew = 2ns, and Tval = 2ns,
there is no reason you can't have a Tprop = 24ns. The values listed for
these timing characteristics in the PCI2.2 spec are because we typically
design one part of the PCI net while the other part lies on a plugin card
we have no control over. By providing numbers to which we can design we
eliminate the unknown.
"The time is always right to do what is right" - MLK Jr
Critical Net Team - Dept. HDC
IBM Rochester, MN
(507) 253-0194 t/l: 553-0194
>Hi SI people,
>When measuring a real PCI bus signal (not 25ohm test load);
>Would the starting point of Tprop be for a rising
>edge in this case at 0.285Vcc?
>Why Tprop isn't measured like in a TDR for example?
>Could this be possible in a 'known' system;
>I would know exactly which PCI devices are going to be
>connected to the bus.
>I would have for example;
>clock skew of 2ns
>setup time 2ns
>Would Tprop of 24ns in this case be possible
>for a 33MHz system?
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