From: Ken Cantrell ([email protected])
Date: Wed Nov 01 2000 - 08:57:57 PST
Salvador,
Sorry for the confusion. The long story made short, judging from the
responses, is that it is common practice in the computer industry to do what
you are talking about (thanks to A. Ingrahm for enlightening me). Schedule
and cost dictate this type of work around. It's not the right way to do it,
it is the cost effective way to accomplish the task. I still maintain that
this is due to inadequate planning in the development stage, and should be
expressed as an SI banner in the design meetings. If we don't all push this
concept, we'll be cleaning up messes forever. No one gets it right the
first time, but why repeat the mistake?
Michael,
Perhaps you should have read the whole thread. At any rate, I was talking
about whether or not stitching the two lines together constituted
parallelism, which it does not (anyone care to enlighten me if I'm
incorrect?). Termination is required. Please review the thread in that
light. I have responded to your specifics below in *text*.
Ken
From: Michael Nudelman [mailto:[email protected]]
Sent: Tuesday, October 31, 2000 3:45 PM
To: Ken Cantrell
Cc: [email protected]; [email protected]
Subject: Re: [SI-LIST] : Parallel single-ended traces routed to achieve
35 Ohm controlledimpedance
Ken,
> Salvador,
> .......One of the obvious problems you
> will have is modulated Zo going from 70 to 35. Your acceptance function
> will only be 0.5, so you will only see a little over half the voltage at
the
> receiver.
Well, this is not entirely true. I did not watch the whole discussion, and
maybe
there are some initial conditions/driver data involved, but in general case
for
a strong driver you'll see more than half and for whimpy one - less than
half.
*Yes, I concurr. I was generalizing.*
BUT - even if it is half-signal - if it is point-to-point trace with no end
termination, than your half-signal will double at the end and you are OK.
*This won't work if you require first incident switching*
> Paralleling two TL's isn't like paralleling two resistors.
Well, yes it is. TL for a driver is nothing but a resistor.
*Well, no it isn't. It's a complex impedence where the propagation function
is frequency dependent. Dr. Johnson's book elaborates on this well.*
> All
> you will add with your stitching the two lines together is more ringing
from
> the via inductance, more crosstalk from the mutual inductance, and a
slight
> increase in Zo. The impedence seen by either separate drivers or a single
> driver driving the two lines will be 70 ohms.
No. The impedance for two lines of 70 Ohm n parallel WILL BE 35 Ohm.
* I'm still talking about an unterminated line, and whether or not stitching
the traces together constitutes parallelism.*
> .....For example, you may not be able to source that
> much current with the present driver, and may need to go to an AC
> termination scheme, or you might have to switch to a stronger driver, or
you
> might have to do both.
Again: AC termination requires more peak driving current from driver than
split
DC one - the "pre-history" helps driver to put up just half the necessary
peak
driving current, while in AC termination for unbalanced signal (it is
however
different for balanced signals, like clocks) requires full swing.
*Well, you got me here. I'm conceptually jumping around as much as you.
I'll work on it. Put an "or" in for that first "and", and you'll catch the
my drift.*
Dr. Johnson's book elaborates on this well....
Salvador:
If your skew is not that important (I understand, your signal is not GHz,
but
somewhat slower) and you can afford few tens of picoseconds - than
everything
you have to do is provide paths of reasonably equal lengths of 70 Ohms each,
each one referenced to the same GND Plane from different sides; this way you
eliminate mutual coupling and will get practically 35 Ohm Ch. Impedance.
If you use different GND planes - do not forget to provide return path GND
via
when jumping layers.
*Mutual inductive coupling will depend on whether or not the traces are
stitched. I don't know of a case where skew is not important, especially in
a tens of picoseconds timing window; otherwise I concurr.*
The via reflection may not be that bad.
*Depends on the number and size of the vias and the edge rate. It could
just as easily have a pronounced effect.*
Also: If you know your driver output impedance and can match it to create
source
termination for your 35 Ohm line - and you are point-to-point (no stubs
etc) -
than just drop end terminator, use only source and you are going to get full
swing signal et thet end of your traces.
*As long as the increase in risetime (approx. 2.2 x) doesn't violate the
timing window. Kind of hard to accomplish that with a 10's of picoseconds
window.*
Mike.
> If you are doing an engineering look see, this
> should get you there, but I wouldn't recommend it for a manufactured
> product.
> Ken
>
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of
> [email protected]
> Sent: Tuesday, October 31, 2000 11:26 AM
> To: Ken Cantrell
> Cc: [email protected]
> Subject: RE: [SI-LIST] : Parallel single-ended traces routed to achieve
> 35 Ohm controlledimpedance
>
> Hello Ken,
>
> We have developed clock-driver circuit that benefits from low impedance
> lines.
> We have tested it in our older system and works well. We decided to add a
> test
> trace to our new backplane and test the circuit on the new system down the
> line.
> The backplane's primary design constraints (no. of layers, dielectric
> material &
> thickness, trace geometry, etc.) were dictated by other application
> requirements
> and performance objectives. So, now we want to fit this trace (if
possible)
> and
> our board house is recommending we run two 70 Ohm traces in parallel. I
> just
> want to make sure we do this right --once.
>
> You are incorrect in quickly assuming there was not enough upfront design
to
> do
> this right. Remember that every time you design a PCB one places priority
> on
> different parts or aspects of your design and normally other constraints
> come
> into play (over-all thickness, SI of other more important nets, pcb cost,
> fabrication issues, etc., etc.). You know where I'm going with this....
>
> All I ask for is: Would some one like to share their knowledge (and
results)
> in
> regards to routing a 70 ohm trace on one set of layers and another of the
> same
> type on a different set of layers so tha when connected at the ends (and
in
> between at even intervals) so that their parrallel impedance is 35 Ohms?
>
> Picture this (SIDE VIEW):
> _________________________________________ GND Layer
> dielectric material
> +=========+=========+===========+ <-----Signal layer 70 ohm impdance
> trace
> | | | |
> | | | | dielectric material
> _ | _______ | _______ | _________ | _____ GND Layer
> | | | |
> +=========+=========+===========+ <-----Signal layer 70 ohm impdance
> trace
> \
> vias dielectric material
> _________________________________________ GND Layer
>
> "Ken Cantrell" <[email protected]> on 10/31/2000 10:18:06 AM
>
> Sent by: "Ken Cantrell" <[email protected]>
>
> To: Salvador Aguinaga/MW/US/3Com, "Michael Nudelman"
> <[email protected]>
> cc: [email protected]
> Subject: RE: [SI-LIST] : Parallel single-ended traces routed to achieve
35
> Ohm
> controlledimpedance
>
> Sounds like the cart is before the horse. I would ask why 35 ohms in the
> first place. Then if that is a valid requirement, you need to design your
> stack up so that you will get 35 ohms across all layers of the board. If
> other signals require a Zo of 70 ohms, and these particular traces require
> 35 ohms, it sounds like there was not enough upfront design going on
during
> layout. Going back to the drawing board may be the fastest way to resolve
> your problem.
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]]On Behalf Of
> [email protected]
> Sent: Friday, October 27, 2000 2:28 PM
> To: Michael Nudelman
> Cc: [email protected]
> Subject: Re: [SI-LIST] : Parallel single-ended traces routed to achieve
> 35 Ohm controlledimpedance
>
> I need to run the trace through the a pin field. The room between pins is
> 2mm
> and because of the dielectric thickness constraint I can only run a single
> 12
> mil wide line through the pin field. If I use a single 35 ohm line, the
> trace
> width is too large to fit through the pin field.
>
> Thanks,
> -- Sal
>
> Michael Nudelman <[email protected]> on 10/27/2000 03:10:31 PM
>
> Sent by: Michael Nudelman <[email protected]>
>
> To: Salvador Aguinaga/MW/US/3Com
> cc: [email protected]
> Subject: Re: [SI-LIST] : Parallel single-ended traces routed to achieve
35
> Ohm
> controlledimpedance
>
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