RE: [SI-LIST] : Decoupling caps selection

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From: Hall, Stephen H (stephen.h.hall@intel.com)
Date: Tue Oct 31 2000 - 09:58:10 PST


There are many answers to your question. It really depends on what you are
trying to decouple and what your circuitry looks like. For something like a
chipset (for example), the most important decoupling issue from a signal
integrity point of view on a bus is the I/O ring. The local power delivery
system must be robust enough to supply the high frequency current demanded
by the fast switching rates of the buffers. In this case, I look at the
transient return currents generated by a single output buffer and estimate
how much of this current will be forced to flow through the local decoupling
network. Lets call this current "Ibuffer". Then I look at the number of
decoupling caps in relation to the number of I/O cells in the particular bus
I am analyzing. Lets assume that there are 2 decoupling caps per I/O cell
(this number is usually limited by the layout). Then I would assume that
each decoupling capacitor would be required to support a transient current
of 2*Ibuffer (this would be deltaI in my previous email). This, obviously,
is just one example of how you can estimate deltaI. If you are providing
decoupling for something like a processor core, I would get an estimate of
the maximum dI/dT from the silicon designers for the part. Then you could
divide this total current by the number of individual caps you have on the
board to get an estimate of deltaI. However, when designing the decoupling,
be certain that you look at the capacitance you have on the die. If you
ignore the capacitance on the die (assuming it is significant) than you may
over-design your decoupling network, which will increase the cost of the
system.

Again, using this type of analysis does not prevent the total C of the I/O
ring and all the series L's from combining in a big tank circuit and
resonating. After you have determined the minimum C and max allowable L,
make certain that you look at the entire circuit and identify any potential
resonance issues. In today's high speed interfaces, this is not a
particular easy thing to do.

I sure hope that this helps.

 -- Steve

-----Original Message-----
From: michael.g.mcdermott@delphiauto.com
[mailto:michael.g.mcdermott@delphiauto.com]
Sent: Tuesday, October 31, 2000 3:23 AM
To: SI List (E-mail)
Subject: RE: [SI-LIST] : Decoupling caps selection

How do you determine the transient current of an IC? (step 2 below)

"Hall, Stephen H" <stephen.h.hall@intel.com> on 10/30/2000 01:39:03 PM

Please respond to "Hall, Stephen H" <stephen.h.hall@intel.com>

To: "'Ravinder Ajmani/San Jose/IBM'" <ajmani@us.ibm.com>
      Dilpreet Saini <DSAINI@altera.com>
cc: "SI List (E-mail)" <si-list@silab.eng.sun.com> (bcc: Michael G
      McDermott/DELCO)

Subject: RE: [SI-LIST] : Decoupling caps selection

Here is a way to estimate the minimum allowable capacitance and the maximum
allowable series inductance (path and lead inductance) when choosing
decoupling capacitors to support high frequency power delivery. This has
been used to decouple large I/O rings that drive high slew rates (like on a
chipset). It has produced good results.

First, estimate the minimum amount of capacitance required.

1. Determine the amount of noise your circuit can tolerate due to power
supply oscillations ... this is deltaV

2. Estimate the transient current that will be flow through the capacitor.
This is deltaI.

3. This gives us an impedance target of deltaV/deltaI, which is the
impedance target for the decoupling cap.

4. Approximate the transient frequency that the capacitor must pass as
F(tran_slow)=0.35/Tr(slow). Where T(slow) is the slowest edge rate you will
expect in your system. It is important to use the slowest edge rate in this
estimation because a capacitor will pass high frequencies. Subsequently,
the use of the slowest edge rate will yield a slightly larger capacitance
value which will ensure the impedance remains low enough for all edge rates,
including the fast ones.

5. The approximate minimum capacitance value is C(min)=
deltaI/(2*pi*F(tran_slow)*deltaV)

Now the maximum tolerable inductance must be estimated ...

6. Determine the transient frequency of the fastest edge you expect to see
in your system. The fastest edge rate is used because inductors will pass
low frequencies. F(tran_fast)=0.35/Tr(fast)

7. Estimate the maximum tolerable series inductance of your cap. This
includes the lead inductance and the inductive path from the die to the
capacitor (be sure to include the inductance of via, planes ...etc).
L(max)= deltaV/(2*pi*F(tran_fast)*deltaI)

This will provide a good estimate for a decoupling capacitors minimum C and
maximum L. Note, however, that this estimation method does not account for
any power delivery resonance issues that can occur when you have a whole
bunch of these capacitors in parallel. The capacitors, in combination with
the series inductance of the leads, vias, planes, bond wires etc. can
resonate like a tank circuit. Be sure to look at the whole decoupling
strategy and try to eliminate the possibility of an unexpected resonance
that will ruin your signal integrity. This analysis is most useful for
decoupling near the chip, because it is much easier to estimate the amount
of transient current that will be forced to flow though the capacitor.

I hope that this helps.

Steve Hall
Intel Corp.

-----Original Message-----
From: Ravinder Ajmani/San Jose/IBM [mailto:ajmani@us.ibm.com]
Sent: Monday, October 30, 2000 8:40 AM
To: Dilpreet Saini
Cc: SI List (E-mail)
Subject: Re: [SI-LIST] : Decoupling caps selection

Dilpreet,
A decoupling capacitor has to supply the peak current demand of the chip.
If I is the peak current demand then:

          I = C*dV/dT

Where C is the capacitance value, dV is the drop in the supply voltage that
can be tolerated, based on the noise margin of the circuit, and dT is the
rise time of the output. As you can see, this expression does not depend
on the frequency of the output. This expression can be used as a rule of
thumb to calculate the number of decoupling capacitors required for a chip.
A more detailed calculation will also involve inductance of the power
supply, size of bulk capacitors, power plane inductance, capacitor
inductance, etc.

Regards, Ravinder
PCB Development and Design Department
IBM Corporation - Storage Systems Division
Email: ajmani@us.ibm.com
***************************************************************************
Always do right. This will gratify some people and astonish the rest.
.... Mark Twain

Dilpreet Saini <DSAINI@altera.com>@silab.eng.sun.com on 10/27/2000 03:14:48
PM

Please respond to Dilpreet Saini <DSAINI@altera.com>

Sent by: owner-si-list@silab.eng.sun.com

To: "SI List (E-mail)" <si-list@silab.eng.sun.com>
cc:
Subject: [SI-LIST] : Decoupling caps selection

Hi all,
     I was wondering if the selection of the decoupling capacitor of a
circuit is MAINLY governed by the edge rates of the switching signals or by
the frequency of their switching. I believe the answer is later cause all
the documentation that I have seen on the dcoupling cap selection so far do
not have any mention of the edge rates. Most of the capacitor manufacturer
have "Impedance Vs Frequency" charts in their specs/catalogs. I am assuming
that the Frequency that they are referring to is the frequency of operation
of the circuit. Any ideas/comments are greatly appreciated.

Dilpreet

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From: "Hall, Stephen H" <stephen.h.hall@intel.com>
To: "'Ravinder Ajmani/San Jose/IBM'" <ajmani@us.ibm.com>,
   Dilpreet Saini
      <DSAINI@altera.com>
Cc: "SI List (E-mail)" <si-list@silab.eng.sun.com>
Subject: RE: [SI-LIST] : Decoupling caps selection
Date: Mon, 30 Oct 2000 10:39:03 -0800
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