Re: [SI-LIST] : Possible TDR microstrip measurement error?

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From: Perry Qu (perry.qu@alcatel.com)
Date: Tue Oct 31 2000 - 07:34:35 PST


Hi! John:

We had the similar situation here when we try to match our field solver
predicted impedance with the manuafacturer's value. Sometime we saw difference
as high as 10 -12 %. We do take into account plating thickness and the solder
mask. However, it seems that it does not change impedance results much for
microstrip line, or more accurately, embedded microstrip. We did not consider
trapezoidal effect of traces though. What's your comment about variation that
these factors can have on the impedance calculation ? Do you use Ansoft 2D for
this purpose ?

Thanks.

Perry Qu

"Lusk, John B" wrote:

> I must agree with John and disagree with Lum....consideration of both solder
> mask and building up of outer layers due to the plated through hole process
> MUST be considered for accurate stack-up characterization. I have seen cases
> where the the combination of solder mask effects and the "thicker" (in
> height) traces causes the overall Zo of the TL to vary by as much as 12%
> from the case without these considerations.
>
> Eric has brought up a subject that we have discussed in my group for quite
> some time. How do we accurately predict what we'll eventually be getting
> from the board house for incorporation into pre-route simulations early on
> in the design? I have worked with several board vendors on correlating their
> stack up proposals and what my field solvers gives me (with varying degrees
> of success). One of the key learnings I have had is that you need to work
> with the vendor to find out *exactly* what the cross section of the stack up
> is. This includes the above mentioned solder mask thickness, plating
> effects, trapezoidal etching, etc. Each board manufacturer should have an SI
> guru. Go directly to him/her for answers instead of spending time with the
> people who merely plug and chug numbers for proposal generation. In doing
> this I have always been able to come to terms with a stack up proposal (once
> I had all the information).
>
> More specific to Eric's statement...microstrip correlation between field
> solvers and vendors proposals do seem to be more difficult than stripline. I
> don't know why this is. Obviously, there is empirical data that is vendor
> specific that must be input into the proposal generation process somewhere.
> However, no empirical data should cause the resulting Zo to differ from the
> "theoretical" field solver solution by more that 5% or so. I know I will
> take heat from some process people out there for saying this, but reality
> should not deviate from theory by more than ~5% (my old college professors
> would be so proud of me).
>
> Interesting side note.....I have personally witnessed board houses TDRing
> test coupons laying flat on a work bench and using this data to determine
> the lot's Zo and tolerance. I know that the microstrip traces they were
> probing that were face down on that bench were definitely being affected by
> the effective dielectric of the table.
>
> Here's a question I have to this panel, specifically toward any members of
> the audience that may work in the board manufacturing industry. Instead of
> providing us with a simple stack up proposal that contains little more
> information than line width, tolerances, and Zo, why not provide us with a
> full set of RLGC parameters instead. This would make my life a lot easier.
> Of course, this would require a big investment on their part, but I believe
> that future high speed designs will need this type of information early on
> in the design process.
>
>
> Thanks for your comments
> John
>
>
> Message-----
> From: Lum Wee Mei [mailto:lweemei@dso.org.sg]
> Sent: Friday, October 27, 2000 12:16 AM
> To: JNH; Eric Bogatin; si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Possible TDR microstrip measurement error?
>
> Lum Wee Mei wrote:
>
> JNH wrote:
>
>
>
> Eric,
>
> For microstrip line measurement, I think we need to consider the solder
> mask, covering the microstrip line with 0.7~1.0 mils thickness. So, the
> microstrip line is an embeded microstrip line not pure microstrip. I use
> the polar tool -- CITS25 to do calculate the microstrip and substrate 2~3
> ohms to compensate the effect of solder mask. The TDR measurment shows
> bigger deviation for microstrip line than that of stripline. I believe it is
> caused by more processing needed for the outer layers of a PCB, such as
> solder platting and solder mask. A 0.5 oz (0.7mils) thickness copper will
> finally be added up to 2.0 mils for the outer layers.
>
>
>
> Best Regards,
>
> John Lin
> SI Engineer, ARD4
> Quanta Computer Inc.,Taiwan, R.O.C.
> Email: John@quantatw.com
> Tel: 886+3+3979000 ext. 5183
>
> -----Original Message-----
> From: Eric Bogatin [ mailto:eric@bogent.com <mailto:eric@bogent.com> ]
> Sent: Friday, October 27, 2000 5:17 AM
> To: Sun. COM
> Cc: eric
> Subject: [SI-LIST] : Possible TDR microstrip measurement error?
>
> After a recent talk I gave on TDR measurements, I was approached by a fellow
>
> from the IPC (I apologize that I did not catch your name, whoever you were),
>
> with a problem that might be common in the board fab industry. I wanted to
> get comments from folks on the SI list as to whether you have encountered
> this problem or is it so obvious that everyone knows to watch out for it.
>
> In some shops, a TDR is used to measure the dielectric constant of the board
>
> material using test lines on coupons. Given the physical length, L, and the
> time delay, TD, for the one way trip (i.e., 1/2 the time measured by the TDR
>
> for an open terminated line), the speed of light in the material can be
> calculated as vel = L/TD. The dielectric constant is calculated as sqrt(2.99
>
> x 10^8 m/sec / vel). This is the straight forward part.
>
> When the trace is a stripline, the dielectric constant extracted is the bulk
>
> dielectric constant of the material surrounding the traces. This value could
>
> be put in a field solver to use to help predict the design rules for traces
> made with this material. I have had success in predicting board trace
> impedance to better than 2% with some field solvers, limited to how well I
> knew the cross section and dielectric constant.
>
> However, when the test line is a microstrip, some of the field lines are in
> air, and the dielectric constant calculated in this way is the "effective"
> dielectric constant, not the board's bulk dielectric constant. Yet, I am
> told some board shops use this measurement from microstrips to get a value
> for what they think is the bulk dielectric constant of their material and
> then use this value in a field solver or approximation. Of course, their
> predictions from the field solver- anyone's- would be off by as much as
> 10%-20%, for the measured impedance of the test lines. I suspect this is the
>
> basis for the comments I have heard that some fab shops are not happy with
> their field solvers- that they have had to add their own correction factors
> to the many approximations that are out there and each shop has their own
> oracle they consult to design a controlled impedance board.
>
> There is still value in the effective dielectric constant. >From the
> microstrip test line cross section, a 2D field solver can be used to extract
>
> what bulk dielectric constant the material under the trace must have had to
> result in the measured effective dielectric constant. If the board shop used
>
> this extracted value for the bulk dielectric constant, their following field
>
> solver results would probably be much more accurate.
>
> has anyone else encountered this problem in board shops?
>
> all comments are welcome.
>
> --eric
>
>
> Eric Bogatin
> BOGATIN ENTERPRISES
> Training for Signal Integrity and Interconnect Design
> v: 913-393-1305
> f: 913-393-1306
> e: eric@bogent.com
> web: < http://www.bogatinenterprises.com/
> <http://www.bogatinenterprises.com/> >
> ftp: ftp://ftp.BogatinEnterprises.com <ftp://ftp.BogatinEnterprises.com>
>
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>
> While I agreed that soldermask has to be considered, whatever plating added
> to the base copper should never be taken as part of the thickness in
> impedance calculation. I may be wrong, then.
>
> Regards - Wee Mei
>
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