From: Chuck Hill ([email protected])
Date: Mon Oct 30 2000 - 08:45:56 PST
See my comments below:
At 10:02 AM 10/30/00 -0500, Ingraham, Andrew wrote:
> > has anyone used a spread spectrum zero clock drivers ?
>Have not personally used them yet, but many others have.
>(What is a "zero clock driver"? If you mean "zero skew", I don't think it
>makes sense to put "spread spectrum" and "zero skew" in the same sentence,
>since the former generates skew by its very nature.)
> > any thing important
> > one has to know before using it ?
>By definition, they generate jitter. Just understand the impact of that on
>all downstream clock consumers.
> > how will such a driver handle a regular clock (non-modulated)?.
>Um, I think that is how you are supposed to use them! If you fed a
>modulated clock into one of them, the results might be "interesting", though
>not necessarily a disaster. Or it might not be much different than what
>you'd get with a non-modulated input.
> > to my
> > understanding, in such
> > case it will act as any other PLL, but will be more susceptible to input
> > clock noise/jitter
> > due to its higher BW. am I correct ?
>Why do you say they have a higher BW? If anything, one could reason that a
>"spread spectrum" clock generator must have a somewhat narrow PLL loop BW,
>so that it doesn't constantly correct its own modulation.
A clock source without spread spectrum clocking is not frequency
modulated. Adding a frequency modulation capability provides an additional
path for unwanted signals (noise) to frequency modulate the output (which
>Any PLL that is downstream of the "spread spectrum" clock driver would need
>to have high BW, so that it would track as closely as possible the jitter on
A PLL downstream really doesn't have to have "high" BW if the phase
modulation doesn't have abrupt changes in phase (and the frequency
modulation is at relatively low frequency). The tracking of that
downstream PLL depends on its loop bandwidth and the modulation
waveform. If the modulation waveform doesn't have abrupt changes in phase,
the downstream PLL can be made to track very accurately without a high loop BW.
Chuck Hill, consultant
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