Re: [SI-LIST] : Decoupling caps selection

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From: Ravinder Ajmani/San Jose/IBM (ajmani@us.ibm.com)
Date: Mon Oct 30 2000 - 08:40:25 PST


Dilpreet,
A decoupling capacitor has to supply the peak current demand of the chip.
If I is the peak current demand then:

          I = C*dV/dT

Where C is the capacitance value, dV is the drop in the supply voltage that
can be tolerated, based on the noise margin of the circuit, and dT is the
rise time of the output. As you can see, this expression does not depend
on the frequency of the output. This expression can be used as a rule of
thumb to calculate the number of decoupling capacitors required for a chip.
A more detailed calculation will also involve inductance of the power
supply, size of bulk capacitors, power plane inductance, capacitor
inductance, etc.

Regards, Ravinder
PCB Development and Design Department
IBM Corporation - Storage Systems Division
Email: ajmani@us.ibm.com
***************************************************************************
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Dilpreet Saini <DSAINI@altera.com>@silab.eng.sun.com on 10/27/2000 03:14:48
PM

Please respond to Dilpreet Saini <DSAINI@altera.com>

Sent by: owner-si-list@silab.eng.sun.com

To: "SI List (E-mail)" <si-list@silab.eng.sun.com>
cc:
Subject: [SI-LIST] : Decoupling caps selection

Hi all,
     I was wondering if the selection of the decoupling capacitor of a
circuit is MAINLY governed by the edge rates of the switching signals or by
the frequency of their switching. I believe the answer is later cause all
the documentation that I have seen on the dcoupling cap selection so far do
not have any mention of the edge rates. Most of the capacitor manufacturer
have "Impedance Vs Frequency" charts in their specs/catalogs. I am assuming
that the Frequency that they are referring to is the frequency of operation
of the circuit. Any ideas/comments are greatly appreciated.

Dilpreet

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